LTC6952 datasheet(37/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

INTRODUCTION

A PLL is a complex feedback system that may concep-

tually be considered a frequency multiplier. The system

multiplies the frequency input at REF± up to the VCO fre-

quency. The PFD, charge pump, N divider, VCO, and loop

filter form a feedback loop to accurately control the VCO

frequency (see Figure 24). The R divider, output dividers

(Mx), and input frequency fREF are used to set the output

frequency value and resolution, and the external loop filter

is used to set the PLL’s loop bandwidth, BW.

APPLICATIONS INFORMATION

75Ω

30Ω

10nF

VCO–

VCO+

REF

M0 DIV, DDEL,

and ADEL

RDIV

NDIV

KPFD

OUT0

OUT10

M10 DIV, DDEL,

and ADEL

KVCO

LF(s)

M1 DIV, DDEL,

and ADEL

OUT1

LTC6952

(fOUT0)

(fOUT1)

(fOUT10)

fREF

fPFD

(fVCO)

ICP

÷R

÷N

÷M0

÷M1

÷M10

6952 F24

Figure 24. PLL Loop Diagram

OUTPUT FREQUENCY

When the loop is locked, the frequency fVCO (in Hz)

produced at the output of the VCO is determined by the

reference frequency fREF, and the R and N divider values,

given by Equation 3:

fVCO = fREF • N/R

(3)

The PFD frequency fPFD is given by the following equation:

fPFD = fREF/R

(4)

and fVCO may be alternatively expressed as:

fVCO = fPFD • N

(5)

N = fVCO/fPFD

(6)

The output frequency fOUTx produced at the output of the

Mx dividers is given by Equation 7:

fOUTx = fVCO/Mx

(7)

Using Equation 3 and Equation 7, the output frequency

resolution fSTEPx produced by a unit change in N is given

by Equation 8:

fSTEPx = fREF/(R • Mx)

(8)

LOOP FILTER DESIGN

A stable PLL system requires care in designing the external

loop filter. Optimum phase noise and spurious performance

can be obtained by using the third-order loop filter shown

in Figure 24.

The loop design should use the following algorithm:

1. Determine the output frequencies fOUTx based on ap-

plication requirements. Using Equation 3, Equation

4, and Equation 7, change fREF, N, R and Mx until the

application frequency constraints are met. Use the

minimum R value that still satisfies the constraints.

2. Select the open loop bandwidth BW constrained by

fPFD. A stable loop requires that BW is less than fPFD

by at least a factor of 10.

3. Select loop filter component RZ and charge pump cur-

rent ICP based on BW and the VCO gain factor, KVCO.

BW (in Hz) is approximated by the following equation:

≅ ICP • RZ • KVCO/(2 • π • N)

(9)

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