LTC6952 datasheet(75/80 Pages) AD

75 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TYPICAL APPLICATIONS

Step 1: Reference Alignment at Daughter Card Inputs

Step 2: ParallelSYNC Multichip Clock Alignment

Step 3: SYSREF Alignment

Step 3: SYSREF PULSES

Stage 2 LTC6952 Phase Noise vs Stage 1 LTC6953 ADEL Setting fOUT = 4GHz, Mx = 1

STAGE 1 ADEL ADJUSTMENTS

REF EDGE ALIGNED < ±5.5ps

(ADJUSTS FOR PART, CABLE & PCB MISMATCH)

5ns/DIV

CARD #1

CARD #2

CARD #3

CARD #4

CARD #5

6952 TAO3b

500ps/DIV

OUT8: 4GHz

CARD #1

OUT1: 500MHz

CARD #1

OUT8: 4GHz

CARDS #2–5

OUT1: 500MHz

CARDS #2–5

6952 TAO3c

SYSREF Valid

Clock Edge

500ps/DIV

OUT0: SYSREF

12.5MHz

OUT1: CLOCK

500MHz

OUT7: SYSREF

12.5MHz

OUT8: CLOCK

4GHz

6952 TAO3d

100ns/DIV

SYSREF

300mV/DIV

6952 TAO3e

RMS JITTER = 73fs

EQUIVALENT ADC SNR METHOD

STAGE 1 ADEL=0

STAGE 1 ADEL=31

STAGE 1 ADEL=63

OFFSET FREQUENCY (Hz)

10k

100k

10M 40M

–180

–170

–160

–150

–140

–130

–120

–110

–100

6952 TAO3f

LTC6952 Datasheet(PDF) 75 Page - Analog Devices

LTC6952 Datasheet(HTML) 75 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL