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LTC6952 Datasheet(PDF) 33 Page - Analog Devices |
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LTC6952 Datasheet(HTML) 33 Page - Analog Devices |
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33 / 80 page  LTC6952 33 6952f For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA OPERATION Table 19. Serial Port Register Contents ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT h00 UNLOCK LOCK LOCK VCOOK VCOOK REFOK REFOK R h01 INVSTAT x[6] x[5] x[4] x[3] x[2] x[1] x[0] R/W hAA h02 PDALL PDPLL PDVCOPK PDREFPK BST FILTR FILTV POR R/W h08 h03 PD3[1] PD3[0] PD2[1] PD2[0] PD1[1] PD1[0] PD0[1] PD0[0] R/W h00 h04 PD7[1] PD7[0] PD6[1] PD6[0] PD5[1] PD5[0] PD4[1] PD4[0] R/W h00 h05 TEMPO 0 PD10[1] PD10[0] PD9[1] PD9[0] PD8[1] PD8[0] R/W h00 h06 RAO PARSYNC 0 LKWIN LKCT[1] LKCT[0] RD[9] RD[8] R/W h0C h07 RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] R/W h01 h08 ND[15] ND[14] ND[13] ND[12] ND[11] ND[10] ND[9] ND[8] R/W h00 h09 ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] R/W h2D h0A CPRST CPUP CPDN CP[4] CP[3] CP[2] CP[1] CP[0] R/W h93 h0B CPMID CPWIDE CPINV EZMD SRQMD SYSCT[1] SYSCT[0] SSRQ R/W h86 h0C MP0[4] MP0[3] MP0[2] MP0[1] MP0[0] MD0[2] MD0[1] MD0[0] R/W h00 h0D SRQEN0 MODE0[1] MODE0[0] OINV0 DDEL0[11] DDEL0[10] DDEL0[9] DDEL0[8] R/W h00 h0E DDEL0[7] DDEL0[6] DDEL0[5] DDEL0[4] DDEL0[3] DDEL0[2] DDEL0[1] DDEL0[0] R/W h00 h0F ADEL0[5] ADEL0[4] ADEL0[3] ADEL0[2] ADEL0[1] ADEL0[0] R/W h00 h10 MP1[4] MP1[3] MP1[2] MP1[1] MP1[0] MD1[2] MD1[1] MD1[0] R/W h00 h11 SRQEN1 MODE1[1] MODE1[0] OINV1 DDEL1[11] DDEL1[10] DDEL1[9] DDEL1[8] R/W h00 h12 DDEL1[7] DDEL1[6] DDEL1[5] DDEL1[4] DDEL1[3] DDEL1[2] DDEL1[1] DDEL1[0] R/W h00 h13 ADEL1[5] ADEL1[4] ADEL1[3] ADEL1[2] ADEL1[1] ADEL1[0] R/W h00 h14 MP2[4] MP2[3] MP2[2] MP2[1] MP2[0] MD2[2] MD2[1] MD2[0] R/W h00 h15 SRQEN2 MODE2[1] MODE2[0] OINV2 DDEL2[11] DDEL2[10] DDEL2[9] DDEL2[8] R/W h00 h16 DDEL2[7] DDEL2[6] DDEL2[5] DDEL2[4] DDEL2[3] DDEL2[2] DDEL2[1] DDEL2[0] R/W h00 h17 ADEL2[5] ADEL2[4] ADEL2[3] ADEL2[2] ADEL2[1] ADEL2[0] R/W h00 h18 MP3[4] MP3[3] MP3[2] MP3[1] MP3[0] MD3[2] MD3[1] MD3[0] R/W h00 h19 SRQEN3 MODE3[1] MODE3[0] OINV3 DDEL3[11] DDEL3[10] DDEL3[9] DDEL3[8] R/W h00 Multidrop Configuration Several LTC6952s may share the serial bus. In this multidrop configuration, SCLK, SDI, and SDO are com- mon between all parts. The serial bus master must use a separate CS for each part and ensure that only one device has CS asserted at any time. It is recommended to attach a high-value resistor to SDO to ensure the line returns to a known level during Hi-Z states. Serial Port Registers The memory map of the LTC6952 may be found in Table 19, with detailed bit descriptions found in Table 20. The register address shown in hexadecimal format under the “ADDR” column is used to specify each register. Each register is denoted as either read-only (R) or read-write (R/W). The register’s default value on device power-up or after a reset is shown at the right. Note that bit 6 in register h05 and bit 5 in register h06 MUST ALWAYS be set to 0. The read-only register at address h00 is used to determine different status flags. These flags may be instantly output on the STAT pin by configuring register h01. See “STAT Output” section below for more information. The register at address h38 is a read-only byte for device identification. |
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