LTC6952 datasheet(31/80 Pages) AD

31 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

Single Byte Transfers

The serial port is arranged as a simple memory map, with

status and control available in 56, byte-wide registers. All

data bursts are comprised of at least two bytes. The 7 most

significant bits of the first byte are the register address,

with an LSB of “1” indicating a read from the part, and

LSB of “0” indicating a write to the part. The subsequent

byte, or bytes, is data from/to the specified register ad-

dress. See Figure 18 for an example of a detailed write

sequence, and Figure 19 for a read sequence.

Figure 20 shows an example of two write communication

bursts. The first byte of the first burst sent from the serial

bus master on SDI contains the destination register ad-

dress (ADDRX) and an LSB of “0” indicating a write. The

next byte is the data intended for the register at address

ADDRX. CS is then taken high to terminate the transfer.

The first byte of the second burst contains the destination

The next byte on SDI is the data intended for the register

at address ADDRY. CS is then taken high to terminate the

transfer.

A6 A5 A4 A3 A2

7-BIT REGISTER ADDRESS

Hi-Z

MASTER–CS

MASTER–SCLK

MASTER–SDI

LTC6952–SD0

A1 A0

0 D7 D6 D5 D4 D3 D2 D1 D0

8 BITS OF DATA

0 = WRITE

6952 F18

16 CLOCKS

A6 A5 A4 A3 A2

7-BIT REGISTER ADDRESS

Hi-Z

A1 A0

D6 D5 D4 D3 D2 D1 D0 DX

8 BITS OF DATA

1 = READ

6952 F19

MASTER–CS

MASTER–SCLK

MASTER–SDI

LTC6952–SDO

16 CLOCKS

Figure 18. Serial Port Write Sequence

Figure 19. Serial Port Read Sequence

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