LTC6952 datasheet(48/80 Pages) AD

48 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

JESD204B DESIGN EXAMPLE USING EZSync MULTI-

CHIP

This design example consists of a system of four JESD204B

analog-to-digital converters (ADCs), four JESD204B

digital-to-analog converters (DACs), and a JESD204B

compatible FPGA. All of the data converters (ADCs and

DACs) and the FPGA require JESD204B subclass 1 defined

device clocks and SYSREFs, and the FPGA requires an

extra management clock. Additionally, the ADCs require

a low noise clock of less than 100fs total RMS jitter. This

leads to a total of 19 separate signals to generate, with

NDIV

RDIV

SYNC AND

SYSREF CTRL

M10

REF

SSRQ BIT

SYNC AND

SYSREF CTRL

M10

SSRQ BIT

IN±

EZS_SRQ±

ADC0

SYSREF

CLK

ADC1

SYSREF

CLK

SYSREF

CLK

ADC2

ADC3

DEV CLK

SYSREF

MGMT CLK

FPGA

SYSREF

CLK

DAC3

SYSREF

CLK

DAC2

DAC1

DAC0

LTC6952

CONTROLLER

LTC6953

FOLLOWER

VCO

LF(s)

VCO±

EZS_SRQ±

INPUT/OUTPUT TERMINATIONS AND

AC COUPLING CAPS NOT SHOWN

6952 F32

frequencies listed below. For this example, the SYSREF

frequencies for all devices are the same and should output

four pulses upon a SYSREF request rising edge:

fADC-CLK = 500MHz

fDAC-CLK = 4000MHz

fFPGA-CLK = 125MHz

fFPGA-MGMT = 100MHz

fSYSREF = 12.5MHz

Figure 32. Block Diagram for JESD204B EZSync Multi-Chip Design Example

LTC6952 Datasheet(PDF) 48 Page - Analog Devices

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