LTC6952 datasheet(55/80 Pages) AD

55 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Putting the ICs into a Lower Power Mode (Optional)

If desired, both ICs can be placed into lower power modes

while awaiting a SYSREF request. This is achieved by set-

ting PDx = 2 for all SYSREF-defined outputs. This powers

down the output driver circuitry but leaves the internal

divider running and in the correct phase relationship to

the clocks.

Performing a SYSREF Request

To produce SYSREF pulses, write a “1” to SRQMD and

take the parts out of low power mode (if used) by writing

all the SYSREF output PDx bits to “0”. Wait 50µs to allow

APPLICATIONS INFORMATION

circuitry to power up. Send the SYSREF request by writing

a “1” to the CONTROLLER SSRQ bit in Reg0B:

CONTROLLER Reg0B = h05

After waiting a minimum of 1ms, write Reg0B again:

CONTROLLER Reg0B = h04

Place the ICs back into low power mode if desired by writing

a “0” to SRQMD and setting PDx = 2 for all SYSREF-defined

outputs. After the rising edge of the SYSREF request, the

SYSREF outputs will pulse four times and then return to a

“0” state as shown in Figure 34. Note that the FOLLOWER

SYSREF pulses may not start and stop at exactly the same

time as the CONTROLLER’s. This is not an issue, since the

SYSREF edges will still be aligned correctly.

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

FOLLOWER DRIVER

(OUT8)

SYNC PASSTHROUGH

(OUT9)

tPD

ADC SYSREFs

(MUTED OUT0, 2, 4 AND 6)

DAC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

FOLLOWER OUTPUTS

CONTROLLER OUTPUTS

DAC SYSREFs

(MUTED OUT3, 5, 7 AND 9)

FPGA SYSREF

(MUTED OUT1)

FPGA MANAGEMENT CLOCK

(OUT 2)

SYSREF VALID CLOCK EDGE

NOT SYNCHRONIZED, PHASE UNDETERMINED

6952 F33

FPGA DEVICE CLOCK

(OUT2)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT0, 2, 4 AND 6)

INTERNAL DAC SYSREF DIVIDERS

(MUTED OUT3, 5, 7 AND 9)

INTERNAL FPGA SYSREF DIVIDER

(MUTED OUT1)

EZS_SRQ or SSRQ BIT

Figure 33. Outputs after Synchronization for the EZSync Multi-Chip Design Example (SRQMD=0)

LTC6952 Datasheet(PDF) 55 Page - Analog Devices

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