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LTC6952 Datasheet(PDF) 59 Page - Analog Devices |
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LTC6952 Datasheet(HTML) 59 Page - Analog Devices |
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59 / 80 page  LTC6952 59 6952f For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA Determining Output Modes All outputs can be programmed as clocks (MODEx = 0), SYSREFs (MODEx = 1 or 3), or SYNC/SRQ passthrough outputs (MODEx = 2) using each output’s individual MODEx bits as described in Table 13, Table 14, and Table 15. Any output can also be programmed to ignore SYNC and SYSREF requests by setting that output’s SRQENx bit to “0”. Noting that this design example calls for pulsed SYSREFs (MODEx = 3) and that the FPGA management clock should always be free running (SRQENx = 0), Table 30 summarizes each output’s mode settings. Table 30. Output Mode Settings for ParallelSync Example IC OUTPUT PURPOSE SRQENx MODEx PDx OUT0 LTC6952 #1 REF 1 0 0 OUT1 LTC6952 #1 EZS-SRQ 1 2 0 OUT2 LTC6952 #2 REF 1 0 0 OUT3 LTC6952 #2 EZS-SRQ 1 2 0 OUT4-10 Unused 0 0 3 OUT0 Unused 0 0 3 OUT1 ADC0 SYSREF 1 3 0 OUT2 ADC0 CLK 1 0 0 OUT3 ADC1 SYSREF 1 3 0 OUT4 ADC1 CLK 1 0 0 OUT5 ADC2 SYSREF 1 3 0 OUT6 ADC2 CLK 1 0 0 OUT7 ADC3 SYSREF 1 3 0 OUT8 ADC3 CLK 1 0 0 OUT9 Unused 0 0 3 OUT10 FPGA MGMT CLK 0 0 0 OUT0 Unused 0 0 3 OUT1 FPGA SYSREF 1 3 0 OUT2 FPGA DEV CLK 1 0 0 OUT3 ADC4 SYSREF 1 3 0 OUT4 ADC4 CLK 1 0 0 OUT5 ADC5 SYSREF 1 3 0 OUT6 ADC5 CLK 1 0 0 OUT7 ADC6 SYSREF 1 3 0 OUT8 ADC6 CLK 1 0 0 OUT9 ADC7 SYSREF 1 3 0 OUT10 ADC7 CLK 1 0 0 APPLICATIONS INFORMATION Determining Output Divider Values Since the desired frequencies of each output are already known, the output divider values can be calculated using Equation 7. Note that the reference LTC6953 EZS_SRQ passthrough outputs’ internal dividers should be set as shown in Table 18. The results are shown in Table 31. Table 31. Output Divide Settings for ParallelSync Example IC OUTPUT PURPOSE Frequency (MHz) Divide Value (Mx) OUT0 LTC6952 #1 REF 122.88 2 OUT1 LTC6952 #1 EZS-SRQ 122.88 2 OUT2 LTC6952 #2 REF 122.88 2 OUT3 LTC6952 #2 EZS-SRQ 122.88 2 OUT4-10 Unused N/A N/A OUT0 Unused N/A N/A OUT1 ADC0 SYSREF 9.216 320 OUT2 ADC0 CLK 294.912 10 OUT3 ADC1 SYSREF 9.216 320 OUT4 ADC1 CLK 294.912 10 OUT5 ADC2 SYSREF 9.216 320 OUT6 ADC2 CLK 294.912 10 OUT7 ADC3 SYSREF 9.216 320 OUT8 ADC3 CLK 294.912 10 OUT9 Unused N/A N/A OUT10 FPGA MGMT CLK 98.304 30 OUT0 Unused N/A N/A OUT1 FPGA SYSREF 9.216 320 OUT2 FPGA DEV CLK 147.456 20 OUT3 ADC4 SYSREF 9.216 320 OUT4 ADC4 CLK 294.912 10 OUT5 ADC5 SYSREF 9.216 320 OUT6 ADC5 CLK 294.912 10 OUT7 ADC6 SYSREF 9.216 320 OUT8 ADC6 CLK 294.912 10 OUT9 ADC7 SYSREF 9.216 320 OUT10 ADC7 CLK 294.912 10 |
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