LTC6952 datasheet(18/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

REFERENCE DIVIDER (R)

A 10-bit divider is used to reduce the frequency seen at

the phase/frequency detector (PFD). Its divide ratio R may

be set to any integer from 1 to 1023. Use the RD[9:0] bits

found in registers h06 and h07 to directly program the R

divide ratio. See the Applications Information section for

the relationship between R and the fREF, fPFD, fVCO, and

fOUTx frequencies.

A mode to provide synchronization of the Reference inputs

to the R divider output (R ≥ 2) using the rising edge of

the EZS_SRQ± pins is enabled when the PARSYNC bit in

for output alignment in ParallelSync Mode, as described

later in this section. The EZS_SRQ± rising edge must meet

setup and hold timing to the rising edge of the Reference

input. See Figure 2 for the timing relationships between

the Reference input, EZS_SRQ± and the R divider output.

Note that changing the R divider output edge timing will

force the PLL to lose phase lock but will return to normal

operation after several loop time constants. See Reference

Signal and EZS_SRQ Timing for ParallelSync Mode in the

Applications Information section for the timing require-

ments of EZS_SRQ± to REF in this mode.

OPERATION

EZS_SRQ±

REF

6952 F02

1 REF CYCLE

tSH

R DIV

tSS

Figure 2. EZS_SRQ± to REF Timing (PARSYNC = 1)

PHASE/FREQUENCY DETECTOR (PFD)

The phase/frequency detector (PFD), in conjunction with

the charge pump, produces source and sink current pulses

proportional to the phase difference between the outputs

of the R and N dividers. This action provides the necessary

feedback to phase-lock the loop, forcing a phase align-

ment at the PFD’s inputs. The PFD may be disabled with

the CPRST bit which prevents UP and DOWN pulses from

being produced. See Figure 3 for a simplified schematic

of the PFD.

RST

N DIV

RST

CPRST

DOWN

6952 F03

DELAY

R DIV

Figure 3. Simplified PFD Schematic

LOCK INDICATOR

The lock indicator uses internal signals from the PFD to

measure phase coincidence between the R and N divider

output signals. It is enabled by programming LKCT[1:0]

in the serial port register h06 (see Table 5), and produces

LOCK, LOCK and UNLOCK status flags, available through

both the STAT output and serial port register h00. LOCK

is the logical inverse of LOCK.

The user sets the phase difference lock window time tLWW

for a valid LOCK condition with the LKWIN bit found in

different fPFD frequencies. See the Applications Informa-

tion section for examples.

Table 4. LKWIN Programming

LKWIN

tLWW

fPFD

3ns

> 5MHz

10ns

≤ 5MHz

The PFD phase difference must be less than tLWW for the

COUNTS number of successive counts before the lock

indicator asserts the LOCK flag. The LKCT[1:0] bits are

used to set COUNTS depending upon the application.

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