LTC6952 datasheet(58/80 Pages) AD

58 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Design Procedure

The design procedure for ParallelSync is similar to EZSync:

1. Determine R and N divider values for all ICs

2. Determine the optimum loop bandwidth(s)

3. Select loop filter component values

4. Determine output modes for all ICs

5. Determine all M divider values

6. Determine all digital delay values

7. Program the ICs with the correct divider values, output

delays, and other settings

8. Synchronize the reference distribution part (if neces-

sary)

9. Synchronize the parallel LTC6952 outputs

10. Place the SYSREF outputs in a lower power mode

until the next SYSREF request (optional, see Opera-

tions section)

11. Place ICs into SYSREF request mode (SRQMD=1) and

send a SYSREF request when needed

12. Return IC into SYNC mode (SRQMD=0) and place the

SYSREF outputs into a lower power mode for power

savings (optional).

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed, or if the divider is

powered down.

Determining R and N Divider Values

The reference LTC6953 does not have a PLL, so R and N

do not apply. However, it can divide the incoming refer-

ence so that it falls below the 167MHz upper limit for the

parallel parts’ fPFD. In this example, the output dividers

of the reference clock outputs of the reference LTC6953

can be set to 2, leading to an effective reference frequency

of 122.88MHz for the parallel parts. Following the “Loop

Filter Design” algorithm for the two parallel LTC6952s, R

should be 1 noting that maximizing fPFD in a data converter

application will minimize integrated jitter. Use Equation 4

to determine fPFD and Equation 6 to determine N:

R = 1

fPFD = fREF/R = 122.88MHz

N = fVCO/fPFD = 24

Selecting Loop Bandwidth

The next step in the algorithm is choosing the open loop

bandwidth for the parallel LTC6952s. The maximum BW

should be at least 10x smaller than fPFD. Most data con-

verter applications will place the bandwidth at the optimal

intersection of VCO noise and in-band noise. Narrower

bandwidths or higher order loop filters can be used to

lower spurious power. For this example, the third-order

loop filter shown in Figure 24 will be used.

After inputting the external VCO phase noise and KVCO

characteristics, the LTC6952Wizard reports the thermal

noise optimized loop bandwidth is approximately 38kHz.

Loop Filter Component Selection

For the lowest in-band phase noise, ICP should be set to

the highest value possible that results in practical loop

filter component values. Therefore, ICP for our example

is chosen to be 11.2mA. LTC6952Wizard uses Equation

9 to determine RZ:

RZ = 2 • π • 38k • 24/(11.2m • 15M)

RZ = 34.1 Ω ≈ 34

The LTC6952Wizard uses Equation 10 through 13 to

calculate CI, CP, C2, and R1:

CI = 4/(π • 38k • 34) = 985nF ≈ 1.0µF

CP = 1/(12 • π • 38k • 34) = 20.5nF ≈ 22nF

C2 = 1/(18 • π • 38k • 34) = 13.7nF ≈ 15nF

R1 = 34Ω

Note that resistors are rounded to standard ±1% values,

and capacitors are rounded to standard ±10% values.

LTC6952 Datasheet(PDF) 58 Page - Analog Devices

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