LTC6952 datasheet(47/80 Pages) AD

47 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

EZS_SRQ OR SSRQ BIT

ADC DEVICE CLOCKS

(OUT1 AND 3)

ADC SYSREFs

(MUTED OUT0 AND 2)

DAC DEVICE CLOCKS

(OUT8 AND 10)

DAC SYSREFs

(MUTED OUT7 AND 9)

FPGA SYSREF

(MUTED OUT4)

FPGA MANAGEMENT CLOCK

(OUT6)

SYSREF VALID CLOCK EDGE

NOT SYNCHRONIZED, PHASE UNDETERMINED

6952 F30

FPGA DEVICE CLOCK

(OUT5)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT0 AND 2)

INTERNAL DAC SYSREF DIVIDERS

(MUTED OUT7 AND 9)

INTERNAL FPGA SYSREF DIVIDER

(MUTED OUT4)

EZS_SRQ OR SSRQ BIT

6952 F31

ADC DEVICE CLOCKS

(OUT1 AND 3)

ADC SYSREFs

(OUT0 AND 2)

DAC DEVICE CLOCKS

(OUT8 AND 10)

DAC SYSREFs

(OUT7 AND 9)

FPGA SYSREF

(OUT4)

FPGA MANAGEMENT CLOCK

(OUT6)

FPGA DEVICE CLOCK

(OUT5)

500MHZ

4000MHZ

125MHZ

100MHZ

Figure 30. Outputs after Synchronization for the EZSync Standalone Design Example (SRQMD=0)

Figure 31. Outputs after SYSREF Request for the EZSync Standalone Design Example (SRQMD = 1)

LTC6952 Datasheet(PDF) 47 Page - Analog Devices

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