LTC6952 datasheet(24/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Table 13. Synchronization (SRQMD = 0) Output Behavior vs Device Settings for with PLL Enabled (PDPLL = 0)

SRQENx

PARSYNC

MODEx

Internal Divider

Sync to Other

Dividers

Internal Divider

Sync to RDIV

Internal Divider Start Latency

from SYNC Signal Falling

Edge (DDELx = 0)

Output Behavior

N/A

Free Running

1, 2, or 3

Muted

Yes

~45µs + R/fREF + 8/fVCO

Mute on SYNC High, Run on

SYNC Low

1 or 3

Muted

SYNC Signal Pass Through

Yes

(x + R)/fREF + 8/fVCO*

Mute on SYNC High, Run on

SYNC Low

1 or 3

Muted

SYNC Signal Pass Through

* Latency depends on the duration of the SYNC pulse, specifically x = floor (tSYNC × fREF - 1) mod R. All outputs will be synchronized correctly regardless of x

Table 14. Synchronization (SRQMD = 0) Output Behavior vs Device Settings for with PLL Disabled (PDPLL = 1)

SRQENx

PARSYNC

MODEx

Internal Divider

Sync to Other

Dividers

Internal Divider

Sync to RDIV

Internal Divider Start Latency

from SYNC Signal Falling

Edge (DDELx = 0)

Output Behavior

N/A

Free Running

1, 2, or 3

Muted

Yes

~45µs + 7/fVCO

Mute on SYNC High, Run on

SYNC Low

1 or 3

Muted

SYNC Signal Pass Through

Yes

7/fVCO

Mute on SYNC High, Run on

SYNC Low

1 or 3

Muted

SYNC Signal Pass Through

OPERATION

The LTC6952 supports three different methods of SYSREF

generation as described in the JESD204B specification:

•

Free Running

•

Gated On/Off by a SYSREF Request Signal

•

One, Two, Four, or Eight SYSREF Pulses After the

Rising Edge of a SYSREF Request Signal

These modes are defined by each output’s individually pro-

grammableMODExbits.InordertogenerateSYSREFpulses,

bit SRQMD must be set to “1” as shown in Table 12, and MPx

must be greater than 0. SYSREF requests (SYSREQ) are

applied on the EZS_SRQ± pins or by setting the SSRQ bit to

“1” (unless PARSYNC = 1). Table 15 describes the output

behavior in SYSREF generation mode. Bits SYSCT[1:0]

can be found in register h0B.

Note that synchronization MUST be completed prior to

SYSREF generation as described in the Synchronization

Overview.

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