LTC6952 datasheet(64/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Performing a SYSREF Request

To produce SYSREF pulses, write a “1” to SRQMD in both

of the parallel LTC6952s and take the parts out of low

power mode (if used) by writing all the SYSREF output

PDx bits to “0”. Wait 50µs to allow the circuitry to power

up. Send the SYSREF request by writing a “1” to the REF

LTC6952’s SSRQ bit in Reg0B:

REF LTC6952 Reg0B = h05

After waiting a minimum of 1ms, write Reg0B again:

REF LTC6952 Reg0B = h04

If desired, the EZS_SRQ± pins of the reference LTC6952

can be used instead of the SSRQ bit to request a SYSREF.

After the rising edge of the SYSREF request, the SYSREF

outputs will pulse four times and then return to a “0”

state as shown in Figure 37. Place the ICs back into low

power mode if desired by writing a “0” to SRQMD in the

parallel LTC6952s and setting PDx = 2 for all SYSREF

defined outputs.

EZS_SRQ OR SSRQ BIT

ON REFERENCE LTC6953

LTC6952 #2 OUTPUTS

LTC6952 #1 OUTPUTS

6952 F37

ADC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

ADC SYSREFs

(OUT3, 5, 7 AND 9)

ADC SYSREFs

(OUT0, 2, 4 AND 6)

FPGA SYSREF

(OUT1)

FPGA MANAGEMENT CLOCK

(OUT2)

FPGA DEVICE CLOCK

(OUT2)

294.912MHz

147.456MHz

98.304MHz

294.912MHz

REFERENCE SOURCE CONSIDERATIONS

A high quality signal must be applied to the REF± inputs as

they provide the frequency reference to the entire PLL. As

mentioned previously, to achieve the part’s in-band phase

noise performance, apply a sine wave of at least 6dBm

into 50Ω, or a square wave of at least 0.5VP-P, with slew

rate of at least 20V/µs.

The LTC6952 may be driven single-ended from CMOS

levels (greater than 2.7VP-P). Apply the reference signal at

REF– , and bypass REF+ to GND with a 47pF capacitor. The

BST bit must also be set to “0”, according to guidelines

given in Table 2. Setting FILT to a “0” is recommended as

the input is a square wave.

The LTC6952 achieves an in-band normalized phase

noise floor LNORM = –229dBc/Hz typical. To calculate its

equivalent input phase noise floor LIN, use Equation 19.

LIN = LNORM + 10 • log10(fREF)

(19)

For example, using a 10MHz reference frequency gives

an input phase noise floor of –159dBc/Hz. The reference

frequency source’s phase noise must be at least 3dB better

thanthistopreventlimitingtheoverallsystemperformance.

Figure 37. Outputs after SYSREF Request for the ParallelSync Design Example (SRQMD=1)

LTC6952 Datasheet(PDF) 64 Page - Analog Devices

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