LTC6952 datasheet(51/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Now that all frequencies are known, use Equation 7 to

determine the output divider values. The results are shown

in Table 26.

Table 26. Output Divide Settings for EZSync Multi-Chip Design

Example

OUTPUT

PURPOSE

Frequency

(MHz)

Divide Value

(Mx)

OUT0

ADC0 SYSREF

12.5

320

OUT1

ADC0 CLK

500

OUT2

ADC1 SYSREF

12.5

320

OUT3

ADC1 CLK

500

OUT4

ADC2 SYSREF

12.5

320

OUT5

ADC2 CLK

500

OUT6

ADC3 SYSREF

12.5

320

OUT7

ADC3 CLK

500

OUT8

FOLLOWER VCO

4000

OUT9

FOLLOWER EZS_SRQ

12.5

320

OUT10

FPGA MGMT CLK

100

OUT0

Unused

N/A

OUT1

FPGA SYSREF

12.5

320

OUT2

FPGA DEV CLK

125

OUT3

DAC0 SYSREF

12.5

320

OUT4

DAC0 CLK

4000

OUT5

DAC1 SYSREF

12.5

320

OUT6

DAC1 CLK

4000

OUT7

DAC2 SYSREF

12.5

320

OUT8

DAC2 CLK

4000

OUT9

DAC3 SYSREF

12.5

320

OUT10

DAC3 CLK

4000

Determining Output Digital Delay Values

The output digital delay is used to control phase rela-

tionships between outputs. The minimum delay step is

½ of a period of the incoming VCO signal. For this design

example, the digital delay is used to place each device’s

SYSREF signal edges into a known phase relationship to its

corresponding device clock, optimized for the set-up (tS)

and hold time (tH) requirements for that device. Assume

that the optimum SYSREF edge location for each device

occurs on the first falling clock edge before the desired

SYSREF valid rising clock edge. In other words, SYSREF

should change states ½ of a corresponding device clock

period before the SYSREF valid device clock edge. Refer

to Figure 29 for a visual example.

APPLICATIONS INFORMATION

For EZSync multi-chip synchronization, the CONTROLLER

output which drives the FOLLOWER VCO input (follower-

driver) must output seven pulses before the FOLLOWER

outputs begin. This means that any CONTROLLER outputs

which should be aligned with the FOLLOWER outputs

(follower-synchronous) must be delayed by the same

amount of time as the seven pulses, leading to a delay

offset for each of these follower-synchronous outputs

(DDELFS-OS):

DDELFS-OS = 14 • MFD + DDELFD

(17)

where MFD and DDELFD are the divider value and digital

delay value, respectively, of the follower-driver. In most

applications, DDELFD will be set to 0.

In order to calculate each output’s delay value for this

design example, use the following procedure:

1. Delay all of the JESD204B device clocks by half of a

period of the slowest JESD204B device clock. This

delay setting is equivalent to the divide value of the

slowest device clock since a one code digital delay

equals half of a VCO cycle. Non-JESD204B clocks (such

as the FPGA management clock) are not included in

this calculation. This delay value defines the desired

SYSREF valid clock edge. In this example, the slowest

JESD204B clock is the FPGA device clock:

DDELSYSvalid = MFPGA-CLK = 32

DDELADC-CLK´ = DDELSYSvalid = 32

DDELDAC-CLK´ = DDELSYSvalid = 32

DDELFPGA-CLK´ = DDELSYSvalid = 32

2. For each device clock/SYSREF pair, subtract half a

device clock period from DDEL to find the SYSREF

delay. This is equivalent to subtracting the correspond-

ing divide value of the device clock, i.e.

DDELADC-SYS´ = DDELSYSvalid – MADC-CLK

DDELADC-SYS´ = 32– 8 = 24

DDELDAC-SYS´ = DDELSYSvalid – MDAC-CLK

DDELDAC-SYS´ = 32– 1 = 31

DDELFPGA-SYS´ = DDELSYSvalid – MFPGA-CLK

DDELFPGA-SYS´ = 32– 32 = 0

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