LTC6952 datasheet(53/80 Pages) AD

53 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Power and FILT Register Programming

For correct PLL operation on the CONTROLLER, all internal

blocks should be enabled. Additionally, the REF and VCO

input signals have a sufficient slew rate and power to not

need the FILT or BST bits:

CONTROLLER Reg02 = h00

The FOLLOWER doesn’t need the FILTV bit either:

FOLLOWER Reg02 = h00

Output Power-Down Programming

During initial setup and synchronization, all used outputs

should be set to full power. These bits will be used later

to place the ICs in a lower power mode while waiting for

SYSREF requests:

CONTROLLER Reg03 = h00

CONTROLLER Reg04 = h00

CONTROLLER Reg05 = h00

FOLLOWER Reg03 = h03

FOLLOWER Reg04 = h00

FOLLOWER Reg05 = h00

RAO and PARSYNC Programming

PARSYNC should be set to “0” for the CONTROLLER since

this example is not a ParallelSync application. RAO should

also be set to “0” unless a highly accurate reference input-

to-clock output timing is required. Note that RAO for the

LTC6953 FOLLOWER is not applicable.

Lock Detect Programming (CONTROLLER Only)

Next, determine the lock indicator window from fPFD.

From Table 4 we see that LKWIN = 0 with a tLWW of 3ns.

The LTC6952 will consider the loop “locked” as long as

the phase coincidence at the PFD is within ±3ns, or 108°

as calculated below.

phase = 360° • tLWW • fPFD

= 360° • 3n • 100M

≈ 108°

APPLICATIONS INFORMATION

Larger values of COUNTS lead to more accurate and stable

lock indications at the expense of longer lock indication

times. A COUNTS value of 2048 will work for this applica-

tion. From Table 5, LKCT[1:0] = 3 for 2048 counts.

R and N Divider Programming

The previously determined R and N divider values for the

CONTROLLER are 1 and 40, respectively. R and N for

the FOLLOWER are not applicable and can be set to 0.

Using these values and the PARSYNC and lock detector

values, registers 6 through 9 can be programmed for the

CONTROLLER:

CONTROLLER Reg06 = h0C

CONTROLLER Reg07 = h01

CONTROLLER Reg08 = h00

CONTROLLER Reg09 = h28

Note that registers 6 through 9 for the LTC6953 FOLLOWER

are not applicable.

Charge Pump Function and Current Programming

Disable all the charge pump functions (CPMID, CPWIDE,

CPRST, CPUP, CPDN, and CPINV), allowing the loop to

lock. Using Table 6 with the previously selected ICP of

11.2mA gives CP[4:0] = h13. The FOLLOWER charge

pump settings are not applicable.

SYNC and SYSREF Global Modes Programming

Bit EZMD controls whether the IC is an EZSync standalone/

controller (“0”) or follower (“1”). Bit SRQMD determines

if the part is in synchronization mode (“0”) or SYSREF

request mode (“1”). SYSCT programs the number of

pulses for any output in pulsed SYSREF mode (# pulses

= 2SYSCT, so SYSCT = 2 to achieve four pulses for this

example). Combining this information with the previously

determined charge pump controls, registers h0A and h0B

can be programmed:

CONTROLLER Reg0A = h13

CONTROLLER Reg0B = h04

FOLLOWER Reg0A = N/A

FOLLOWER Reg0B = h14

LTC6952 Datasheet(PDF) 53 Page - Analog Devices

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