LTC6952 datasheet(49/80 Pages) AD

49 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

To determine which multi-chip configuration to use, we

utilize the flowchart in Figure 15. This example has nine

total JESD204B device clock/SYSREF pairs, four of which

need to be less than 100fs total jitter. We also need one

additional non-low noise standalone clock for the FPGA.

Therefore:

TP = 9

LNP = 4

TS = 1

LNS = 0

Based on these inputs, Figure 15 suggests using the

EZSync Multi-Chip protocol with request passthrough

topology shown in Figure 12, using one CONTROLLER

and one FOLLOWER chip. Noting that the use of LTC6953

for any FOLLOWER chips is recommended, Figure 32

shows a block diagram of the full system. OUT8 of the

CONTROLLER LTC6952 is driving the IN± inputs of the

FOLLOWER LTC6953. This output is referred to as the

“follower-driver” output. OUT9 of the CONTROLLER is

driving the EZS_SRQ± pins of the FOLLOWER, and is

therefore the SYNC/SRQ passthrough output. Also notice

that the CONTROLLER clock outputs are the lowest jitter

clocks, and should therefore be used to drive the ADCs.

Reference and VCO Assumptions

For this example, assume the available reference is a

100MHz sine wave oscillator with 8dBm output power, and

the VCO is a 4000MHz oscillator with a KVCO of 5MHz/V,

output power of 7dBm, and phase noise of –115dBc/Hz

at 10kHz.

fREF = 100MHz

fVCO = 4000MHz

KVCO = 5MHz/V

Design Procedure

Designing and enabling this clock generation solution

consists of the following steps:

APPLICATIONS INFORMATION

1. Determine CONTROLLER R and N divider values

2. Determine the optimum loop bandwidth

3. Select loop filter component values

4. Determine all output modes for CONTROLLER and

FOLLOWER

5. Determine all M divider values

6. Determine all digital delay values

7. Program the ICs with the correct divider values, output

delays, and other settings

8. Synchronize the outputs

9. Place the SYSREF outputs in a lower power mode

until the next SYSREF request (optional, see Opera-

tions section)

10. Place ICs into SYSREF request mode (SRQMD=1) and

send a SYSREF request when needed

11. Return IC into SYNC mode (SRQMD=0) and place the

SYSREF outputs into a lower power mode for power

savings (optional).

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed, or if the divider is

powered down.

Determining CONTROLLER R and N Divider Values

Following the “Loop Filter Design” algorithm, first deter-

mine all the divider values. From the Electrical Charac-

teristics, the maximum fPFD is 167MHz, which is larger

than the fREF of 100MHz. Therefore R should be 1 noting

that maximizing fPFD in a data converter application will

minimize integrated jitter. Use Equation 4 to determine

fPFD and Equation 6 to determine N:

R = 1

fPFD = fREF/R = 100MHz

N = fVCO/fPFD = 40

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