FS6500 datasheet(22/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground.

When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 32).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

VHYST

VHYST = VTH_REC – VTH_DOM

—

0.175

× VSUP

IBUS_NO_GND

Ground disconnection. GND = VSUP, 0 V < VBUS < 18 V, VBAT =

12 V. Loss of local GND does not affect communication in the

remaining network

–1.0

—

1.0

[16]

IBUS_NO_BAT

VBAT disconnection. VSUP = GND, 0 V < VBUS < 18 V. Node

sustains the current which can flow under this condition. BUS

remains operational.

—

µA

LINTSD

LIN thermal shutdown

150

175

—

°C

[5]

LINTSD_HYST

LIN thermal shutdown hysteresis

°C

CLIN

LIN internal capacitor

—

[5]

Table 5. Static electrical characteristics ...continued

[1]

Long duration timer and VKAM disable.

[2]

VSUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE × IPRE.

[3]

VSUP min to guarantee VKAM and main logic supply in LPOFF.

[4]

Guaranteed by characterization.

[5]

Guaranteed by design.

[6]

External PNP gain within 150 to 450.

[7]

Valid for VSUP3 ≥ IO_5.

[8]

If a higher resistor value than recommended is used, the accuracy degrades.

[9]

Wide range accuracy for input voltage from 9.0 V to 19 V.

[10] Guaranteed by design and characterization.

[11] VBAT is the voltage at the input of the control unit.

[12] Current flowing inside the pin. A transceiver must be capable to sink at least 40 mA.

[13] VBAT: voltage across the battery connectors of the vehicle. VGND_ECU: voltage on the local ECU ground connector with respect to battery ground of the

vehicle (VGND_BATTERY).

[14] This constraint refers to duty cycle D1 and D2 only.

[15] VTH_DOM: receiver threshold of the recessive to dominant LIN bus edge. VTH_REC receiver threshold of the dominant to recessive LIN bus edge.

[16] VSUP is the voltage at the input of the device (different from VBAT when a reverse current protection diode is implemented.

10 Dynamic electrical characteristics

TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground.

When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 32).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Digital interface timing

fSPI

SPI operation frequency (50 % DC)

0.5

—

8.0

MHz

tMISO_TRANS

MISO transition speed, 20 – 80 %

• VDDIO = 5.0 V, CLOAD = 50 pF

• VDDIO = 5.0 V, CLOAD = 150 pF

5.0

—

tCLH

Minimum time SCLK = HIGH

—

tCLL

Minimum time SCLK = LOW

—

tPCLD

Propagation delay (SCLK to data at 10 % of MISO rising edge)

—

tCSDV

NCS = low to data at MISO active

—

tSCLCH

SCLK low before NCS low (setup time SCLK to NCS change H/

—

tHCLCL

SCLK change L/H after NCS = low

—

tSCLD

SDI input setup time (SCLK change H/L after MOSI data valid)

—

tHCLD

SDI input hold time (MOSI data hold after SCLK change H/L)

—

Table 6. Dynamic electrical characteristics

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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