FS6500 datasheet(82/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

13 Serial peripheral interface

13.1 High-level overview

13.1.1 SPI

The device uses a 16-bit SPI, with the following arrangement:

MOSI, primary out, secondary in bits:

• Bit 15 read/write

• Bit 14 main or fail-safe register target

• bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, next bit (=0) in read

mode.

• bit7 to 0 (D7 to D0): control bits

MISO, primary in, secondary out bits:

• bits 15 to 8 (S15 to S8) are device status bits

• bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or

device flags.

Figure 69 is an overview of the SPI implementation.

13.1.2 Parity bit 8 calculation

The parity bit 8 is used in write mode only (bit 15 = 1). It is calculated based on the number of logic ones

contained in the bit 15–9, 7–0 sequence (this is the whole 16-bits of the write command except bit 8). In read

mode, the parity bit should be set to 0.

Bit 8 must be set to 0 if the number of ones is odd.

Bit 8 must be set to 1 if the number of ones is even.

13.1.3 Device status on MISO

When a write operation is performed to store data or a control bit in the device, the MISO pin reports a 16-bit

fixed device status composed of two bytes: device fixed status (bits 15 to 8) + extended device status (bits

7 to 0). In a read operation, MISO reports the fixed device status (bits 15 to 8), and the next eight bits are

content of the selected register. A standard serial peripheral interface (SPI) is integrated to allow bidirectional

communication between the FS6500/FS4500 and the MCU. The SPI is used for configuration and diagnostic

purposes.

FS6500-FS4500-ASILD

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Product data sheet

Rev. 8 — 5 August 2024

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FS6500 Datasheet(PDF) 82 Page - NXP Semiconductors