FS6500 datasheet(83/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

aaa-037798

MISO

SCLK signal is low outside of NCS active

NCS active low. Must be raised at end of 16 clocks,

for write commands, MOSI bits [15] = [1].

MOSI and MISO data changed at SCLK rising edge

and sampled at falling edge. MSB first.

MISO tri-state outside of NCS active

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

R/W M/FS

MOSI

Parity

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

data

S15

S14

S13

S12

S11

S10

Device status

Do7

Do6

Do5

Do4

Do3

Do2

Do1

Do0

Extended device status, Register control bits or device flags

NCS

SCLK

MOSI

MISO

Don't care

S15

S14

Do0

Tri-state

Figure 69. SPI overview: SPI waveform and signals polarity

The device contains several registers. Their address is coded on 7 bits (bits 15 to 9). Each register controls

or reports part of the device function. Data can be written to the register, to control the device operation or set

default value or behavior. Every register can also be read back to ensure its content (default setting or value

previously written) is correct.

13.1.4 Register description

Although the minimum time between two NCS low sequences is defined by tONNCS (Figure 9), two consecutive

accesses to the fail-safe registers must be done with a 3.5 µs minimum NCS high time in between. Although the

minimum time between two fail-safe registers accesses is 3.5 µs, some SPI accesses to the main registers can

be done in between (Figure 10).

13.2 Detailed operation

13.2.1 SPI command organization

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bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

R/W

M/FS

MOSI

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

SPI_G

WU_G

CAN_G

LIN_G

IO_G

VPRE_G VCORE_G

MISO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

VOTHERS_G

Bits 15:8 always sent by Main digital

Extended diagnosis: sent by Main or Fail safe based on bits 15:9 on MOSI

Figure 70. MOSI /MISO SPI command organization

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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