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FS6500 Datasheet(PDF) 57 Page - NXP Semiconductors

Part # FS6500
Description  Safety power system basis chip with CAN FD and LIN transceivers
PDF  153 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6500 Datasheet(HTML) 57 Page - NXP Semiconductors

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NXP Semiconductors
FS6500-FS4500-ASILD
Safety power system basis chip with CAN FD and LIN transceivers
When VPRE is set up to work in buck-boost mode, the application can work down to VSUP = VSUP_UV_L = 2.7 V
with a minimum of 300 mA current guaranteed on VPRE. The buck-boost configuration helps to pass the LV124
specification requiring a minimum of 3.2 V on VBAT supply during cold cranking conditions.
aaa-037768
VSUP_UV_7
VSUP_UV_L
VCORE_FB_UV *
((R3+R4)/R4)
Buck
VPRE_EN
VPRE
VSUP
VCORE
INTB
RSTB
Buck_Boost
Mask
Buck
Boost
Boost
Figure 39. Behavior during cranking (buck boost configuration)
12.7.1.3 Light load condition
To improve the converter efficiency and avoid any unwanted output voltage increase, the VPRE voltage
regulator operates in pulse skipping mode during light load conditions.
The transition between normal mode and pulse skipping mode is based on the comparison between the error
amplifier output (EA_out) and pre-defined thresholds VPRE_LL_H and VPRE_LL_L. When the error amplifier output
reaches VPRE_LL_L, the VPRE high-side transistor is switched off. When the error amplifier output reaches
VPRE_LL_H, the VPRE high-side transistor is switched on again for the next switching period (Figure 40).
aaa-037769
error
amplifier
light load
comparator
(Hyst 20 mV)
VPRE HS
driver
Ref
Vpre_LL_L
VPRE
SW_PRE
VSUP1/2
EA_out
EA_out
Vpre_LL_H
Vpre_LL_L
Light load
flag
HS gate
drive
GND
Figure 40. Description of light load conditions
FS6500-FS4500-ASILD
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 8 — 5 August 2024
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