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FS6500 Datasheet(PDF) 45 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers WD Refresh OK / WD Refresh NOK / WD OFF / WD Refresh OK / WD Refresh NOK / WD OFF / Watchdog Refresh Counter WD_CNT_RFR = 6 WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK 0 1 2 3 4 5 6 WD refresh OK aaa-037750 WD Refresh NOK WD Refresh OK / WD Refresh NOK / WD OFF / WD Refresh NOK / WD_OFF Watchdog Refresh Counter WD_CNT_RFR = 4 WD refresh OK WD refresh OK WD refresh OK WD refresh OK 0 1 2 3 4 WD Refresh NOK WD Refresh NOK / WD_OFF Watchdog Refresh Counter WD_CNT_RFR = 2 WD refresh OK WD refresh OK 0 1 2 WD Refresh NOK WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD OFF / Watchdog Refresh Counter WD_CNT_RFR = 1 WD refresh OK 0 1 WD Refresh NOK Figure 21. Watchdog refresh counter configuration (INIT_WD_CNT register, WD_CNT_RFR_1:0) Window CLOSED OPEN BAD key WD_NOK WD_NOK GOOD key WD_NOK WD_OK SPI None (timeout) No_issue WD_NOK Table 11. Watchdog error table Any access to the watchdog register during the ’closed’ watchdog window is considered as a wrong watchdog refresh. Watchdog timeout, meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh. 12.5.3 Fault error counter The fault error counter manages and counts the number of faults occurring in the application. This counter is incremented not only for the fault linked to consecutive wrong refresh watchdogs, but also for other sources of fault (undervoltage, overvoltage, external reset,...). The fault error counter is incremented by 1, each time RSTB and/or FS0B pin is asserted. When FS0B is asserted, the fault error counter is incremented by 1, every time the watchdog error counter maximum value is reached. The fault error counter has two output values (intermediate and final). • The intermediate value can be used to force the FS0B activation or to generate a RSTB pulse depending on the FLT_ERR_IMP_1:0 bit configuration in INIT_FAULT register. • The final value is used to handle the transition to deep fail-safe when the SELECT pin is connected to Ground. If the SELECT pin is connected to VPRE, the main state machine remains in normal mode and the regulators remain on. The intermediate value of the fault error counter is configurable to ’1’ or ’3’ using the FLT_ERR_FS bit in the INIT_FAULT register (Table 83). The final value of the fault error counter is based on the intermediate configuration. This configuration must be done during INIT_FS phase. FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 45 / 153 |
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