FS6500 datasheet(69/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

VSUP_UV_5

VPRE_EN

VPRE

VPRE_UV

VCCA/VAUX

VCORE

120 µs

1.0 ms

16.5 ms typ

256 ms max

VSUP

LBIST

INTB

(VDDIO=VCORE)

select pin

RSTB

UV Lock-out

1.0 ms

aaa-037782

Figure 53. Start-up scheme

The final value of VAUX and VCCA depends on the hardware configuration (resistor values at the SELECT pin).

The typical start-up sequence takes around 16.5 ms to release RSTB. RSTB can be pulled low after those 16.5

ms by the MCU, if it is not ready to run after power up. See Section 12.7.7 for the VKAM start-up sequence.

12.8 Long duration timer

The device includes a long duration timer, with an integrated oscillator. The timer is configurable by the SPI

and can operate in normal mode and low-power mode. It provides several functions and offers a large range of

counting periods, as well as a calibration mechanism, for internal oscillator compensation.

The timer is not part of the safety circuitry, and is not covered by LBIST (logic built in self-test). However it can

be activated in normal mode, and all prescaler options can be selected, to allow timer circuitry verification. The

timer is based on a 24-bit counter, with a 32768 Hz oscillator, allowing a 1.0 s timebase.

FS6500-FS4500-ASILD

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Product data sheet

Rev. 8 — 5 August 2024

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FS6500 Datasheet(PDF) 69 Page - NXP Semiconductors