FS6500 datasheet(47/153 Pages) NXP

47 / 153 page

NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

INCR WD Refresh counter = 7

aaa-037752

POR |

WU from LPOFF

* Assert FS0 if cfg

* Assert RST if cfg

turn off regulators

* DFS if cfg

INCR

WD Refresh counter = 7

RSTB asserted for 8 seconds if cfg

Figure 23. Fault error counter (FLT_ERR_FS = 1, WD_CNT_RFR = 6)

12.5.3.1 Fault error counter intermediate value

Figure 24 illustrates the fault error counter increment when the watchdog error counter maximum value is

reached.

RSTB

delay time

New fully OPEN

window of 256 ms

1st WD refresh OK after

INIT phase. Start of the

WD window

NOK

WD window

WD error

counter

Fault error

counter

RSTB

WD Refresh

counter

aaa-037753

Figure 24. Example of WD operation generating a reset (WD_CNT_ERR = 6)

Figure 25 illustrates the RSTB and FS0B possible behavior at the fault error counter intermediate value

depending on WD_IMPACT_1:0 and FLT_ERR_IMP_1:0 bits configurations:

• #1, WD_IMPACT_1:0 = ’01’ and FLT_ERR_IMP_1:0 = ’01’: WD impact on RSTB only and FS0B is asserted

low if FLT_ERR_CNT ≥ intermediate value

• #2, WD_IMPACT_1:0 = ’10’ and FLT_ERR_IMP_1:0 = ’10’: WD impact on FS0B only and RSTB is asserted

low if FLT_ERR_CNT ≥ intermediate value and WD error counter = WD_CNT_ERR[1:0]

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

Document feedback

47 / 153

FS6500 Datasheet(PDF) 47 Page - NXP Semiconductors

FS6500 Datasheet(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL