FS6500 datasheet(46/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

• FLT_ERR_FS = 0/Intermediate = 3; Final = 6 (Figure 22).

• FLT_ERR_FS = 1/Intermediate = 1; Final = 2 (Figure 23).

In any condition, if the RSTB pin is asserted low for a duration longer than eight seconds, the device goes to:

• Deep fail-safe if the DFS function is enabled (SELECT pin connected to ground)

• LPOFF-sleep if the DFS function is disabled (SELECT pin connected to VPRE)

The following faults lead to an increment of the fault error counter and can be configured:

• Watchdog error counter = max value (6 by default)

• VCORE, VCCA, VAUX undervoltage

• VCORE, VCCA, VAUX overvoltage

• FCRBM follows VCORE configuration

• IO_45 error detection (external IC error)

The following faults lead to an increment of the fault error counter and cannot be configured:

• VPRE overvoltage

• Watchdog refresh not OK or watchdog timeout during INIT phase

• SPI DED

• ABIST1, ABIST2 fail

• RSTB short to high (by cascaded effect of FS0B assertion)

• External reset (except reset extension by MCU after reset assertion by the device)

• IO_23 error detection (FCCU)

INCR

WD Refresh counter = 7 if cfg

aaa-037751

POR |

WU from LPOFF

* Assert FS0 if cfg

* Assert RST if cfg

Turn OFF regulators

* DFS if cfg

INCR = WD error counter = WD_CNT_ERR[1:0] |

WD refresh NOK during INIT_FS |

IO23/45_ERR |

UV/OV/FCRBM |

ABIST1/2 |

RSTB_short_high |

SPI DED |

External Reset |

INCR

WD Refresh counter = 7

WD Refresh counter = 7 if cfg

RSTB assrted for 8 seconds if cfg

* Assert RST if cfg

Figure 22. Fault error counter (FLT_ERR_FS = 0, WD_CNT_RFR = 6)

FS6500-FS4500-ASILD

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Product data sheet

Rev. 8 — 5 August 2024

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