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FS6500 Datasheet(PDF) 61 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 153 page ![]() NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers FB_CORE COMP_CORE FCRBM VCORE VOLTAGE L_VCORE CBOOT_CORE D_VCORE RSNUB_VCORE CSNUB_VCORE R1 R3b R4b R3 R2 GND PGND PGND PGND PGND GND C2 R4 C1 aaa-037773 ESR CAP. < 100 mΩ Figure 44. VCORE buck regulator 12.7.2.2 Light load condition To improve the converter efficiency and avoid any unwanted output voltage increase, the VCORE voltage regulator operates in pulse skipping mode during light load conditions. The principle is the same as the VPRE implementation described in detail in Section 12.7.1.3. 12.7.2.3 Current limitation A current limitation is implemented to avoid uncontrolled power dissipation inside the device (duty cycle control) and limits the current below ICORE_LIM. The current limitation is banked when the pass transistor is switched on during tCORE_BLK_LIM to avoid parasite detection. When the ICORE_LIM threshold is reached, the high-side integrated MOSFET is switched off. The MOSFET is not switched on again before the next rising edge of the switching clock. The current limitation induces a duty cycle reduction and leads to the VCORE output voltage to fall gradually and may cause an undervoltage condition, bringing the device into a fail-safe state. The current limitation does not switch off the regulator. 12.7.2.4 Voltage monitoring The overvoltage detection switches off the regulator. The regulator remains on during an undervoltage detection. Diagnostic is reported in the dedicated register, generates an interrupt, and may bring the application into the fail-safe state, depending on the supervisor configuration (register INIT_VCORE_OVUV_IMPACT). For safety purposes, the FCRBM pin monitors the external resistor bridge (R3/R4) used to set up the final VCORE voltage through a second resistor bridge (R3b/R4b) to detect an external resistor drift or disconnection. The monitoring compares the FB_CORE and FCRBM pins (Figure 45) and triggers when FB_CORE – FCRBM > ±150 mV max. FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 61 / 153 |
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