FS6500 datasheet(87/153 Pages) NXP

87 / 153 page

NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

Address

FS/M

Hex

Write description

Table ref.

DIAG_CAN_LIN

#18(12h)

Read only

Table 54

DIAG_SPI

#19(13h)

Read only

Table 56

NOT USED

#20(14h)

N/A

MODE

#21(15h)

Write during normal and read

Table 58

REG_MODE

#22(16h)

Write during normal and read

Table 60

IO_OUT_AMUX

#23(17h)

Write during normal and read

Table 62

CAN_LIN_MODE

#24(18h)

Write during normal and read

Table 64

NOT USED

#25(19h)

N/A

LDT_AFTER_RUN_1

#26(1Ah)

Write during normal and read

Table 66

LDT_AFTER_RUN_2

#27(1Bh)

Write during normal and read

Table 68

LDT_WAKE_UP_1

#28(1Ch)

Write during normal and read

Table 70

LDT_WAKE_UP_2

#29(1Dh)

Write during normal and read

Table 72

LDT_WAKE_UP_3

#30(1Eh)

Write during normal and read

Table 74

Table 19. Register mapping of main logic ...continued

13.2.5 Fail-safe logic register address table

Table 20 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for fail-safe logic

Address

FS/M A4

Hex

Write description

Table ref.

INIT_FS1B_TIMING

#33(21h)

Write during INIT phase then read only

Table 76

BIST

#34(22h)

Write (No restriction) and read

Table 78

INIT_SUPERVISOR

#35(23h)

Write during INIT phase then read only

Table 80

INIT_FAULT

#36(24h)

Write during INIT phase then read only

Table 82

INIT_FSSM

#37(25h)

Write during INIT phase then read only

Table 84

INIT_SF_IMPACT

#38(26h)

Write during INIT phase then read only

Table 86

WD_WINDOW

#39(27h)

Write (no restriction) and read

Table 88

WD_LFSR

#40(28h)

Write (no restriction) and read

Table 90

WD_ANSWER

#41(29h)

Write (no restriction) and read

Table 92

RELEASE_FSxB

#42(2Ah)

Write (no restriction) and read

Table 94

SF_OUTPUT_REQUEST

#43(2Bh)

Write (no restriction) and read

Table 96

INIT_WD_CNT

#44(2Ch)

Write during INIT phase then read only

Table 98

DIAG_SF_IOs

#45(2Dh)

Read only

Table 100

WD_COUNTER

#46(2Eh)

Read only

Table 102

DIAG_SF_ERR

#47(2Fh)

Read only

Table 104

NOT USED

#48(30h)

N/A

INIT_VCORE_OVUV_IMPACT

#49(31h)

Write during INIT phase then read only

Table 106

INIT_VCCA_OVUV_IMPACT

#50(32h)

Write during INIT phase then read only

Table 108

INIT_VAUX_OVUV_IMPACT

#51(33h)

Write during INIT phase then read only

Table 110

DEVICE_ID_FS

#52(34h)

Read only

Table 112

Table 20. Register mapping of fail-safe logic

13.2.6 Secured SPI command

Some SPI commands must be secured to avoid unwanted change of the critical bits. The secured bits in the

fail-safe machine and the main state machine are calculated from the data bits sent as follows:

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

Document feedback

87 / 153

FS6500 Datasheet(PDF) 87 Page - NXP Semiconductors

FS6500 Datasheet(HTML) 87 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL