FS6500 datasheet(35/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

12.1.1 Buck or buck boost configuration

An external low-side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter.

The connection of the external MOSFET is detected automatically during the start-up phase (after a power-on

reset or from LPOFF).

• If the external low-side MOSFET is not connected (GATE_LS pin connected to PGND), the product is

configured as a standard buck converter.

• If the external low-side MOSFET is connected (GATE_LS pin connected to external MOSFET gate), the

product is configured as a non-inverting buck-boost converter.

The automatic detection is done by pushing 300 μA current on Gate_LS pin and monitoring the corresponding

voltage generated. If a voltage >120 mV is detected before the 120 μs timeout, the non-inverting buck-boost

configuration is locked. Otherwise, the standard buck configuration is locked. The boost driver has a current

capability of ±300 mA.

12.1.2 VPRE on

Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched on and a soft start with a

specified duration tPRE_SOFT controls the VPRE output capacitor charge.

12.1.3 SELECT pin configuration

This phase detects the required voltage level on VAUX and VCCA, according to the resistor value connected

between the SELECT pin and Ground or VPRE, and configures the deep fail-safe function.

12.1.4 VCORE/VAUX/VCCA on

In this stage, the three regulators VCORE, VAUX, VCCA are switched on at the same time with a specified soft

start duration. The CAN_5V is also started at this time.

12.1.5 INIT main

This mode is automatically entered after the device is ’powered on’. When RSTB is released, initialization

phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be

configured in this mode (see Table 19 and Table 20). Other registers can be written in this mode, and also in

normal mode.

Once the INIT registers configurations are complete, a last register called ’INIT_INT’ must be configured to

switch to normal mode. Writing data in this register (even same default values), automatically locks the INIT

registers, and the product switches automatically to normal mode in the main state machine.

12.1.6 Normal

In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by

writing in the INIT_INT register. While in normal mode, the device can be set to low-power mode (LPOFF) using

secured SPI command.

12.1.7 Low-power mode off

The main state machine has three LPOFF modes with different conditions to enter and exit each LPOFF mode,

as described hereafter. After wake-up from LPOFF, all the regulators are enabled by default. In LPOFF, all the

regulators are switched off, except VKAM. The register configuration and the ISO pulse requirement are valid

for the three LPOFF modes.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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