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FS6500 Datasheet(PDF) 41 Page - NXP Semiconductors

Part # FS6500
Description  Safety power system basis chip with CAN FD and LIN transceivers
PDF  153 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6500 Datasheet(HTML) 41 Page - NXP Semiconductors

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NXP Semiconductors
FS6500-FS4500-ASILD
Safety power system basis chip with CAN FD and LIN transceivers
12.5.1 Fail-safe machine state diagram
FLT_err_count = 0
& ABISTx ok & FS_OUT ok
& No activate RSTB
No activate
FSxB
aaa-037746
- RSTB/FSxB asserted low
- RSTB asserted low
- 8 s timer running
- RSTB/FSxB asserted low
- 8 s timer not running
- RSTB released, FSxB asserted low
- 8 s timer running
- Unlock SPI init registers
- 256 ms open window
- RSTB released, FSxB asserted low
- 8 s timer running
- Start WD windowing
- 8 s timer running
- RSTB delay running
- RSTB asserted low
- 8 s timer running
- FSxB asserted low
- FSxB released
- RSTB/FSxB asserted low
- 8 s timer starts (running)
- RSTB/FSxB asserted low
- 8 s timer reset (not running)
- RSTB/FSxB asserted low
- 8 s timer running
-VCORE/VCCA/VAUX OFF-
-VPRE/VCAN OFF-
-RSTB = LOW-
-FSxB = LOW-
- FSxB asserted low
LBIST
Power Down
From
Anywhere
ABIST1
Release
RTSB
Release
FSxB
Wait
VPRE
Wait
VREG
SELECT pin
configuration
LPOFF-
SLEEP
Deep Fail-
save
From anywhere
after LBIST
From INIT_FS
or NORMAL_WD
ABIST2
(VAUX or FS1B)
Assert RSTB
Assert FSxB
INIT_FS
NORMAL_WD
LBIST Done
VPRE > VPRE_UV VPRE < VPRE_UV
IO_0=0
VPRE < VPRE_UV
1 ms elapsed
VCORE > VCORE_UV
& VCCA > VCCA_UV
ABIST1 Done
External
RST
No DFS &
RST delay = 8 s
DFS &
(RST delay = 8 s or
FLT_err_count = 6)
No activate RSTB &
RSTB delay expired
Activate
RSTB
External
RST
WD Not
OK
External
RST
No external RST &
No activate RSTB
WD OK
FLT_err_count=0
& ABISTx ok
& FS_OUT ok
SPI command
SPI command
ABIST Done
ABIST Done
Activate
RSTB
Activate
RSTB
Activate
FSxB
PORB = 1 and
VPRE > VPRE_UV
PORB = 0
Figure 17. Detailed fail-safe state diagram
FS6500-FS4500-ASILD
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 8 — 5 August 2024
Document feedback
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