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FS6500 Datasheet(PDF) 85 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 85 Page - NXP Semiconductors |
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85 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers Description Report a LIN event (diagnostic) 0 No event 1 LIN event LIN_G[4] Reset condition Power on reset/when initial event cleared on read Description Report a change in IOs state 0 No IO transition 1 IO transition IO_G[5] Reset condition Power on reset/when initial event cleared on read Description Report an event from VPRE-REGULATOR and battery monitoring (status change or failure) 0 No event 1 Event occurred VPRE_G[6] Reset condition Power on reset/when initial event cleared on read Description Report an event from VCORE regulator (status change or failure) 0 No event 1 Event occurred VCORE_G[7] Reset condition Power on reset/when initial event cleared on read Description Report an event from VCCA, VAUX, or VCAN regulators (status change or failure) 0 No event 1 Event occurred VOTHERS_G[8] Reset condition Power on reset/when initial event cleared on read Table 17. MISO bits description...continued [1] SPI_G = SPI_ERR or SPI_CLK or SPI_REQ or SPI_PARITY or SPI_FS_ERR or SPI_FS_CLK or SPI_FS_REQ or SPI_FS_PARITY [2] WU_G = IO_5_WU or IO_4_WU or IO_3_WU or IO_2_WU or IO_0_WU or PHY_WU [3] CAN_G = CANH_BATT or CANH_GND or CANL_BATT or CANL_GND or CAN_DOM or RXD_REC or TXD_DOM or CAN_OT or CAN_OC [4] LIN_G = LIN_OT or RXDL_REC or TXDL_DOM or LIN_DOM [5] IO_G = IO_5 or IO_4 or IO_3 or IO_2 or IO_0 [6] VPRE_G = VSNS_UV or VSUP_UV_7 or IPFF or ILIM_PRE or TWARN_PRE or BOB or !VPRE_STATE or VPRE_OV or VPRE_UV [7] VCORE_G = TWARN_CORE or !VCORE_STATE or VCORE_OV or VCORE_UV [8] VOTHERS_G = ILIM_CCA or TWARN_CCA or TSD_CCA or ILIM_CCA_OFF or VCCA_UV or VCCA_OV or ILIM_AUX or TSD_AUX or ILIM_AUX_OFF or VAUX_OV or VAUX_UV or ILIM_CAN or VCAN_UV or VCAN_OV or TSD_CAN 13.2.3 Fail-safe logic general diagnostic aaa-037801 MISO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Extended diagnosis: sent by Main or Fail safe based on bits 15:9 on MOSI SPI_FS_ERR SPI_FS_CLK SPI_FS_REQ SPI_FS_PARITY Figure 72. MISO SPI bits 7:4 FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 85 / 153 |
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