FS6500 datasheet(27/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

aaa-037739

NCS

3.5 µs min

500 ns min

Any Fail-safe

Any main

Figure 10. Register access restriction

11 Functional pin description

11.1 Introduction

The FS6500/FS4500 is the fourth generation of the system basis chip, combining:

• High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN FD and

LIN interfaces.

• External ICs such as sensors, accurate reference voltage for A to D converters, and keep alive memory

supply in low-power mode for MCU static RAM.

• Built-in CAN flexible data interface at 2.0 Mbit/s (ISO 11898-2(12) and -5(13)), and LIN interface (LIN up to Rev.

2.2(22), (23)/SAEJ2602-2(24)), with local and bus failure diagnostic, protection, and fail-safe operation mode.

• Low-power mode, with ultra low-current consumption.

• Various wake-up capabilities.

• Long duration timer available in normal and low-power mode.

• Enhanced safety features with multiple fail-safe outputs and a scheme to support ASIL D applications.

11.2 Power supplies (VSUP1, VSUP2, VSUP3)

VSUP1 and VSUP2 are the input pins for the internal supply dedicated to the SMPS regulators. VSUP3 is the

input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO 7637(14) pulses. VSUP1, 2, and

3 must be connected to the same supply (Figure 73).

11.3 VSENSE input (VSENSE)

This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor.

It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also

includes a resistor divider to measure VSENSE voltage via the MUX-OUT pin. The VSENSE pin is robust

against ISO 7637(14) pulses.

11.4 Pre-regulator (VPRE)

A highly flexible SMPS pre-regulator is implemented in the FS6500/FS4500. It can be configured as a ’non-

inverting buck-boost converter’ (Figure 34) or ’standard buck converter’ (Figure 33), depending on the external

configuration (connection of pin GATE_LS). The configuration is detected automatically during start-up

sequence.

The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated

in the device. The high-side switching MOSFET is also integrated to make the current control easier. The pre-

regulator delivers a typical output voltage of 6.5 V, which is used internally. Current limitation, overcurrent,

overvoltage, and undervoltage detectors are provided. VPRE is enabled by default.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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