FS6500 datasheet(52/153 Pages) NXP

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NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

FS0B

Device and ECU is safe state

FS1B

tDURATION

FS1B automatic release

after tDURATION

FS0B release

by the SPI

FS1B asserted after tDURATION

aaa-037760

Failure detected

Figure 31. tDURATION operation

12.5.7 Fail-safe outputs (FS0B and FS1B) release

When the fail-safe outputs FS0B and consequently FS1B are asserted low by the device due to a fault, some

conditions must be validated before allowing these pins to be released by the device. These conditions are:

• ABIST2_FS1B_OK=1 if part number with FS1B

• ABIST2_VAUX_OK=1 except if VAUX_FS_OV_1:0=VAUX_FS_UV_1:0="00"

• Fault is removed

• Fault error counter must be at ’0’

• Close the S1 switch if FS1B backup delay was engaged (FS1B_DLY_DRV bit = 1)

• RELEASE_FSxB register must be filled with the right value

12.5.7.1 RELEASE_FSxB register

When a fault is removed and the fault error counter changes back to level ’0’, a right word must be filled in the

RELEASE_FSxB register. The value depends on the current WD_LFSR. LSB, MSB must be swapped, and a

negative operation per bit must be applied.

FS0B and FS1B can be released independently or at the same time, depending on the configuration of the first

three bits of the RELEASE_FSxB register (Table 12).The RELEASE_FSxB write command should be done after

a WD_LFSR read command. If FS0B and FS1B are released sequentially, the procedure must be done a first

time for FS0B, and a second time for FS1B.

WD_LFSR_7:0

Release FS0B

RELEASE_FSxB_7:0

Release FS1B

RELEASE_FSxB_7:0

Release FS0B and FS1B

RELEASE_FSxB_7:0

Table 12. RELEASE_FSxB register based on LFSR value

12.5.8 SPI DED

Some SPI registers affect some safety critical aspects of the fail-safe functions, and therefore are required to

be protected against SEU (single event upset). Only fail-safe registers are concerned. During INIT_FS mode,

access to fail-safe registers for product configuration is open. Once the INIT_FS phase is over, the Hamming

circuitry is activated to protect registers content.

At this stage, if there is one single bit flip, the detection is made due to Hamming code, the error is corrected

automatically (fully transparent for the user), and a flag is sent. If there are two errors (DED - dual error

detection), the detection is made due to Hamming code but detected errors cannot be corrected. The flag is

sent and FS0B is activated.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

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