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FS6500 Datasheet(PDF) 86 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers Description Secured SPI communication check, concerns fail-safe logic only. 0 No error 1 Error detected in the secured bits SPI_FS_ERR Reset condition Power on reset Description SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by SPI_ CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) SPI_FS_CLK Reset condition Power on reset Description Invalid SPI access (wrong write or read, write to INIT registers in normal mode, wrong address), concerns fail-safe Logic only 0 No error 1 SPI violation SPI_FS_REQ Reset condition Power on reset Description SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit error SPI_FS_PARITY Reset condition Power on reset Table 18. MISO bits description 13.2.4 Main logic register address table Table 19 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Address Register FS/M A4 A3 A2 A1 A0 Hex Write description Table ref. INIT_VREG 0 0 0 0 0 1 #1(01h) Write during INIT phase then read only Table 22 INIT_WU1 0 0 0 0 1 0 #2(02h) Write during INIT phase then read only Table 24 INIT_WU2 0 0 0 0 1 1 #3(03h) Write during INIT phase then read only Table 26 INIT_INT 0 0 0 1 0 0 #4(04h) Write during INIT phase then read only Table 28 INIT_INH_INT 0 0 0 1 0 1 #5(05h) Write during INIT phase then read only Table 30 LONG_DURATION_TIMER 0 0 0 1 1 0 #6(06h) Write during normal and read Table 32 NOT USED 0 0 0 1 1 1 #7(07h) N/A N/A HW_CONFIG 0 0 1 0 0 0 #8(08h) Read only Table 34 WU_SOURCE 0 0 1 0 0 1 #9(09h) Read only Table 36 DEVICE_ID 0 0 1 0 1 0 #10(0Ah) Read only Table 38 IO_INPUT 0 0 1 0 1 1 #11(0Bh) Read only Table 40 DIAG_VPRE 0 0 1 1 0 0 #12(0Ch) Read only Table 42 DIAG_VCORE 0 0 1 1 0 1 #13(0Dh) Read only Table 44 DIAG_VCCA 0 0 1 1 1 0 #14(0Eh) Read only Table 46 DIAG_VAUX 0 0 1 1 1 1 #15(0Fh) Read only Table 48 DIAG_VSUP_VCAN 0 1 0 0 0 0 #16(10h) Read only Table 50 DIAG_CAN_FD 0 1 0 0 0 1 #17(11h) Read only Table 52 Table 19. Register mapping of main logic FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 86 / 153 |
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