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FS6500 Datasheet(PDF) 84 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 84 Page - NXP Semiconductors |
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84 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers Description Set if it is a read or write command 0 Read R/W 1 Write Description Split the addresses between fail-safe state machine and main logic 0 Main M/FS 1 Fail-safe Description Set the address to read or write 0 A4:0 1 See register mapping Description Parity bit (only use in write mode). Set to 0 in read mode 0 Number of ’1’ (bit 15:9 and bit 7:0) is odd P 1 Number of ’1’ (bit 15:9 and bit 7:0) is even Description Data in write mode. Must be set to 00h in read mode 0 D7:0 1 See register details Table 16. MOSI bits description 13.2.2 Main logic general diagnostic aaa-037800 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 SPI_G WU_G CAN_G LIN_G IO_G VPRE_G VCORE_G MISO VOTHERS_G Bits 15:8 alwayssent by Main digital Figure 71. MISO SPI bits 15:8 Description Report an error in the SPI communication 0 No failure 1 Failure SPI_G[1] Reset condition Power on reset/read Description Report a wake-up event. Logical OR of all wake-up sources 0 No WU_G event 1 WU_G event WU_G[2] Reset condition Power on reset/when initial event cleared on read Description Report a CAN event (diagnostic) 0 No event 1 CAN event CAN_G[3] Reset Condition Power on reset/when initial event cleared on read Table 17. MISO bits description FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 84 / 153 |
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