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FS6500 Datasheet(PDF) 25 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 25 Page - NXP Semiconductors |
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25 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 32). Symbol Parameter Min. Typ. Max. Unit Notes tCORE_UV_R VCORE FB undervoltage reaction time — — 15 µs tCORE_OV VCORE FB overvoltage filtering time 128 — 234 µs tCORE_OV_R VCORE FB overvoltage reaction time — — 314 µs tCCA_UV VCCA undervoltage filtering time 4.0 — 10 µs tCCA_UV_R VCCA undervoltage reaction time — — 15 µs tCCA_OV VCCA overvoltage filtering time 128 — 234 µs tCCA_OV_R VCCA overvoltage reaction time — — 314 µs tAUX_UV VAUX undervoltage filtering time 4.0 — 10 µs tAUX_UV_R VAUX undervoltage reaction time — — 15 µs tAUX_OV VAUX overvoltage filtering time 128 — 234 µs tAUX_OV_R VAUX overvoltage reaction time — — 314 µs Digital input – multi-purpose IOs FIO_IN Digital input frequency range 0.0 — 100 kHz Analog multiplexer tMUX_READY SPI selection to data ready to be sampled on Mux_out • VDDIO = 5.0 V, CMUX_OUT = 1.0 nF — — 10 µs Interrupt tINTB_LG INTB pulse duration (long) 90 100 — µs tINTB_ST INTB pulse duration (short) 20 25 — µs Long duration timer CLKLDT Long duration timer oscillator 31129 32768 34407 Hz CLKLDT_% Long duration timer oscillator accuracy • from –40 °C to 125 °C • from –20 °C to 85 °C and calibration –5.0 –2.0 — — 5.0 2.0 % CAN dynamic characteristics (FD 2.0 Mbit/s) tDOUT TXD dominant state timeout 0.8 — 5.0 ms tDOM Bus dominant clamping detection 0.8 — 5.0 ms tLOOP Propagation loop delay TXD to RXD • RLOAD = 120 Ω, C between CANH and CANL = 100 pF, C at RXD < 15 pF — — 255 ns t1PWU First pulse wake-up time 0.5 — 3.5 µs t3PWU Second and third pulse wake-up time 0.5 — 1.0 µs t3PTO1 Multiple pulse wake-up timeout (short) 100 120 — µs t3PTO2 Multiple pulse wake-up timeout (long) 2400 2800 — µs tCAN_READY Delay to enable CAN by SPI command (NCS rising edge) to CAN to transmit (device in normal mode and CAN interface in TX/RX mode) — — 100 µs [3] tBIT(BUS) Transmitted recessive bit width at 2.0 Mbit/s 435 — 530 ns tBIT(RXD) Received recessive bit width at 2.0 Mbit/s 400 — 550 ns tREC Receiver timing symmetry at 2.0 Mbit/s –65 — 40 ns Table 6. Dynamic electrical characteristics ...continued FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 25 / 153 |
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