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FS6500 Datasheet(PDF) 92 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 92 Page - NXP Semiconductors |
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92 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MISO SPI_G WU_G CAN_G LIN_G IO_G VPRE _G VCORE _G VOTHERS_ G INT_ DURATION INT_INH_ LIN INT_INH_ ALL INT_INH_ VSNS INT_INH_ VPRE INT_INH_ VCORE INT_INH_ VOTHER INT_INH_ CAN Description Define the duration of the interrupt pulse 0 100 µs 1 25 µs INT_DURATION Reset condition Power on reset Description Inhibit the interrupt for LIN error bits 0 All INT sources 1 LIN error bits change INHIBITED INT_INH_LIN Reset condition Power on reset Description Inhibit ALL the interrupt 0 All INT sources 1 All INT inhibited INT_INH_ALL Reset condition Power on reset Description Inhibit the interrupt for VSNS_UV 0 All INT sources 1 VSNS_UV INT inhibited INT_INH_VSNS Reset condition Power on reset Description Inhibit the interrupt for VPRE status event 0 All INT sources 1 VPRE status change inhibited INT_INH_VPRE Reset condition Power on reset Description Inhibit the interrupt for VCORE status event 0 All INT sources 1 VCORE status change inhibited INT_INH_VCORE Reset condition Power on reset Description Inhibit the interrupt for VCCA/VAUX and VCAN status event 0 All INT sources 1 VCCA/VAUX/VCAN status change inhibited INT_INH_VOTHER Reset condition Power on reset Description Inhibit the interrupt for CAN error bits 0 All INT sources 1 CAN error bits change inhibited INT_INH_CAN Reset condition Power on reset Table 29. INIT_INT description and configuration of the bits (default value in bold) FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 92 / 153 |
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