FS6500 datasheet(58/153 Pages) NXP

58 / 153 page

NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

12.7.1.4 Input power feed forward condition

To improve the converter efficiency during high input power conditions, the VPRE switching frequency is

reduced from 440 kHz to 220 kHz, when VSUP > VSUP_IPFF, to decrease the switching losses. The transition

between the two frequencies is transparent for the application.

aaa-037770

VPRE_FSW

VSUP

IPFF

440 kHz

220 kHz

VSUP_IPFF

Figure 41. Input power feed forward principle

12.7.1.5 Overcurrent detection and current limitation

12.7.1.5.1 Overcurrent protection:

To ensure the integrity of the high-side MOSFET, an overcurrent detection is implemented. The regulator is

switched off by the main state machine when the IPRE_OC overcurrent detection threshold is reached three

consecutive times. The overcurrent detection is blanked when the pass transistor is switched on during tPRE_OC

to avoid parasitic switch off of the high-side gate driver.

The VPRE output voltage decrease causes an undervoltage condition on one of the cascaded regulators

(VCORE, VCCA, VAUX) and brings the device into fail-safe state. The overcurrent protects the regulator in case

the SW_PRE pin is shorted to GND. The overcurrent works in buck mode only.

12.7.1.5.2 Current limitation:

A current limitation is also implemented to avoid uncontrolled power dissipation inside the device (duty cycle

control) and limits the current. VPRE current limitation is automatically set based on the buck or buck-boost

configuration. In buck only mode, the lowest current limitation IPRE_LIM2 is applied while in buck-boost mode,

the highest current limitation IPRE_LIM1 is applied. The current limitation is blanked when the pass transistor is

switched on during tPRE_BLK_LIM to allow short-circuit detection on the SW_PRE pin.

When IPRE_LIM threshold is reached during buck mode, the high-side integrated MOSFET is switched off. When

the IPRE_LIM threshold is reached during boost mode, the external low-side MOSFET is switched off. In both

cases, the MOSFET is not switched on again before the next rising edge of the switching clock.

The current limitation induces a duty cycle reduction and leads to the VPRE output voltage gradually dropping,

which may cause an undervoltage condition on one of the cascaded regulators (VCORE, VCCA, VAUX) and

bring the device to the fail-safe state. The current limitation does not switch off the regulator. The current

limitation protects the regulator when the VPRE pin is shorted to GND.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

Document feedback

58 / 153

FS6500 Datasheet(PDF) 58 Page - NXP Semiconductors

FS6500 Datasheet(HTML) 58 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL