FS6500 datasheet(36/153 Pages) NXP

36 / 153 page

NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

12.1.7.1 LPOFF - sleep

Entering in low-power mode LPOFF - sleep is only available if the product is in normal mode by sending a

secured SPI command. In this mode, all the regulators are turned off and the MCU connected to the VCORE

regulator is unsupplied. Only VKAM is available if VKAM is used (specific part number for VKAM on by default).

Once the FS6500/FS4500 is in LPOFF - sleep, the device monitors external events to wake-up and leave the

low-power mode. The wake-up events can occur and depending on the device configuration from:

• Physical layer (CAN or LIN)

• I/O inputs

• Timer

When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE

configuration (buck or buck-boost), the wake-up source is reported to the dedicated SPI register, and the fail-

safe state machine is also restarted.

12.1.7.2 LPOFF - auto WU

LPOFF - auto WU is entered when the device is in the INIT or normal mode and if the VPRE voltage level is

passing the VPRE_UV_4P3 threshold (typ 4.3 V). It can be also entered by sending a secured SPI command if the

product is in normal mode. It allows a POR and complete restart of the fail-safe state machine. After 1.0 ms, the

device attempts to recover by switching on VPRE again.

12.1.7.3 LPOFF - deep FS

LPOFF - deep FS is entered when the device is in deep fail-safe and if the key is off (IO_0 is low). To exit this

mode, a transition to high level on IO_0 is required. IO_0 is usually connected to the key on key off signal (see

Section 12.3).

12.1.7.4 Register configuration in LPOFF

In LPOFF, the register settings of the main state machine are kept because the internal 2.5 V main digital

regulator is available for wake-up operation. However, the register settings of the fail-safe state machine are

erased because the 2.5 V fail-safe digital regulator is not available in LPOFF. As a consequence, after a wake-

up event, the configuration of the fail-safe registers must be done again during initialization phase (256 ms open

window).

12.1.7.5 ISO pulse in LPOFF

If the application has to sustain ISO pulses on VBAT in LPOFF mode, the connection of an external Zener diode

and a serial resistor to the ground is mandatory (see Figure 15). During repetitive ISO pulses on VBAT, the

capacitors connected on VSUP line are more and more charged and cannot be discharged due to the extremely

low-current needed to maintain wake-up capabilities on IOs, CAN, and LIN. As a consequence, if a leakage

path is not created artificially with those discrete components, the voltage on VSUP line can exceed the absolute

maximum rating supported by this pin.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

Document feedback

36 / 153

FS6500 Datasheet(PDF) 36 Page - NXP Semiconductors

FS6500 Datasheet(HTML) 36 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL