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4559 Datasheet(PDF) 102 Page - Renesas Technology Corp

Part # 4559
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  148 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4559 Datasheet(HTML) 102 Page - Renesas Technology Corp

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Rev.1.04
Aug 23, 2007
Page 102 of 146
REJ03B0188-0104
4559 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC
(Skip if Zero, Carry flag )
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
0
0
0
010
11
11 2 02 F 16
11
-
(CY) = 0
Opera-
tion:
(CY) = 0 ?
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag
CY is “0”.
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY
flag is “1”.
SZD
(Skip if Zero, port D specified by register Y)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
0
0
0
010
01
00 2 02 4 16
2
2
-
(D(Y)) = 0
0
0
0
010
10
11 2 02 B 16 Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port D specified by
register Y is “0”. Executes the next instruction when the bit
is “1”.
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are
set to register Y.
Opera-
tion:
(D(Y)) = 0 ?
(Y) = 0 to 5
T1AB
(Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
0
011
00
00 2 23 0 16
11
-
-
Opera-
tion:
(T17
−T14) ← (B)
(R17
−R14) ← (B)
(T13
−T10) ← (A)
(R13
−R10) ← (A)
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of timer 1 and timer 1 reload register R1. Transfers the
contents of register A to the low-order 4 bits of timer 1 and
timer 1 reload register R1.
T2AB
(Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
0
011
00
01 2 23 1 16
11
-
-
Opera-
tion:
(T27
−T24) ← (B)
(R2L7
−R2L4) ← (B)
(T23
−T20) ← (A)
(R2L3
−R2L0) ← (A)
Grouping:
Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
(T27
−T24) of timer 2 and the high-order 4 bits (R2L7−R2L4)
of timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits (T23
−T20) of timer 2 and
the low-order 4 bits (R2L3
−R2L0) of timer 2 reload register
R2.



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