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• All the devices in the stack share a common power-good signal, which must be pulled up to a logic high level

above Vsub(IH_PG). The PG pins must be connected and pulled up, even if the PG output is not used.

• All the devices in the stack share a common compensation signal.

• All secondary devices must connect a 47kΩ resistor between the SYNC_OUT pin and ground.

• The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins

floating).

• Each device must be configured for the same switching frequency.

• The primary device must be configured for forced PWM operation (secondary devices are automatically

configured for forced PWM operation).

• A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.

• Only the VSEL pin of the primary device is used to set the default output voltage. The VSEL pin of secondary

devices is not used and must be connected to ground.

• The SDA and SCL pins of secondary devices are not used and must be connected to ground.

• A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase

offset of approximately 140° relative to the adjacent devices in the daisy-chain. To daisy-chain the clocking

signal, connect the SYNC_OUT pin of the primary device to the MODE/SYNC pin of the first secondary

device. Connect the SYNC_OUT pin of the first secondary device to the MODE/SYNC pin of the second

secondary device. Continue this connection scheme for all devices in the stack, to daisy-chain them together.

• Hiccup overcurrent protection must not be used in a stacked configuration.

In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see Section

7.3.3). Each device in the stack can pull the EN pin low during device start-up or when a fault occurs. Thus, the

stack is only enabled when all devices have completed the start-up sequence and are fault-free. A fault in any

one device disables the whole stack for as long as the fault condition exists.

During start-up, the primary converter pulls the COMP pin low for as long as the enable signal

(SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP

pin and all converters in the stack follow the COMP voltage. During start-up, each device in the stack pulls

the PG pin low while the device initializes. When initialization is complete, each secondary device in the stack

sets the PG pin to a high impedance and the primary device alone controls the state of the PG signal. The PG

pin goes high when the stack has completed the start-up ramp and the output voltage is within specification.

The secondary converters in the stack detect the rising edge of the power-good signal and switch from DCM

operation to CCM operation. After the stack has successfully started up, the primary device controls the power-

good signal in the normal way. In a stacked configuration, there are some faults that only affect individual

devices, and other faults that affect all devices. For example, if one device enters current limit, only that device

is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the

shared enable (SYSTEM_READY) signal.

Functionality During Stacked Operation

Some device features are not available during stacked operation, or are only available in the primary converter.

Table 7-8 summarizes the available functionality during stacked operation.

Table 7-8. Functionality During Stacked Operation

FUNCTION

PRIMARY DEVICE

SECONDARY DEVICE

REMARK

UVLO

Yes

Common enable signal

OVLO

Yes

Common enable signal

OCP – Current Limit

Yes

Individual

OCP – Hiccup OCP

Do not use during stacked

operation.

Thermal Shutdown

Yes

Common enable signal

Power-Good (Window

Comparator)

Yes

Primary device only

I2C Interface

Yes

Primary device only

DVS

Through I2C

Voltage loop controlled by primary

device only

TPS62870, TPS62871, TPS62872, TPS62873

SLVSGC5E – JANUARY 2023 – REVISED OCTOBER 2025

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