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TPS62870 Datasheet(PDF) 42 Page - Texas Instruments |
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TPS62870 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 66 page ![]() 8.4 CONTROL3 Register (Address = 3h) [Reset = 0h] CONTROL3 is shown in Figure 8-4 and described in Table 8-6. Return to the Summary Table. This register controls various device configuration options. Figure 8-4. CONTROL3 Register 7 6 5 4 3 2 1 0 RESERVED SINGLE PGBLNKDVS R-000000b R/W-0b R/W-0b Table 8-6. CONTROL3 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 000000b Reserved for future use. For compatibility with future device variants, program these bits to 0. 1 SINGLE R/W 0b Single operation. This bit controls the internal EN pulldown and SYNC_OUT functions. 0b = EN pin pulldown and SYNC_OUT enabled 1b = EN pin pulldown and SYNC_OUT disabled. Do not use during stacked operation. 0 PGBLNKDVS R/W 0b Power-good blanking during DVS 0b = PG pin reflects the output of the window comparator. 1b = PG pin is high impedance during DVS. TPS62870, TPS62871, TPS62872, TPS62873 SLVSGC5E – JANUARY 2023 – REVISED OCTOBER 2025 www.ti.com 42 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TPS62870 TPS62871 TPS62872 TPS62873 |
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