TPS62870 datasheet(36/66 Pages) TI2

36 / 66 page

Upon the receipt of a stop condition, all devices know that the bus is released, and the devices wait for a start

condition followed by a matching address.

Attempting to read data from register addresses not listed in this section results in 0x00 being read out.

SCL from

Controller

Data Output

by Receiver

Data Output by

Transmitter

Not Acknowledge

Acknowledge

Clock pulse for

acknowledgment

START

Condition

Figure 7-18. Acknowledge on the I2C Bus

SDA

SCL

MSB

ACK

S or Sr

START or

repeated START

condition

acknowledgement

signal from Target

byte complete,

interrupt within target

3 to 8

ACK

clock line held low while

interrupts are serviced

Sr or P

STOP or

repeated START

condition

acknowledgement

signal from receiver

Recognize START or

REPEATED START

condition

Recognize STOP or

REPEATED START

condition

Generate ACKNOWLEDGE

signal

Figure 7-19. Bus Protocol

7.5.3 I2C Update Sequence

The following are required for a single update:

• A start condition

• A valid I2C address

• A register address byte

• A data byte

After the receipt of each byte, the receiving device acknowledges by pulling the SDA line low during the high

period of a single clock pulse. A valid I2C address selects the target. The target performs an update on the falling

edge of the acknowledge signal that follows the LSB byte.

TPS62870, TPS62871, TPS62872, TPS62873

SLVSGC5E – JANUARY 2023 – REVISED OCTOBER 2025

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