TPS62870 datasheet(35/66 Pages) TI2

35 / 66 page

Table 7-10. I2C Interface Target Address Selection (continued)

VSEL PIN

I2C TARGET ADDRESS (1)

Short Circuit to GND

0x41

Short Circuit to VIN

0x42

47kΩ to VIN

0x43

(1)

Available I2C address. This parameter is Device number dependent. Refer to the device options table in Section 4

TI recommends that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of SDA

and SCL pullup voltages to make sure of reset of the I2C engine.

7.5.2 Standard, Fast, Fast Mode Plus Protocol

The controller initiates a data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 7-16. All I2C-compatible devices must

recognize a start condition.

CLK

DATA

START

Condition

STOP

Condition

Figure 7-16. START and STOP Conditions

The controller then generates the SCL pulses, and transmits the 7-bit address and the read and write direction

bit R/W on the SDA line. During all transmissions, the controller makes sure that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 7-17). All

devices recognize the address sent by the controller and compare the address to the internal fixed addresses.

Only the target with a matching address generates an acknowledge (see Figure 7-18) by pulling the SDA line

low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows

that a communication link with a target has been established.

CLK

DATA

Data line stable;

data valid

Change of

data allowed

Figure 7-17. Bit Transfer on the Serial Interface

The controller generates further SCL cycles to either transmit data to the target (R/W bit 0) or receive data

from the target (R/W bit 1). In either case, the target must acknowledge the data sent by the controller. So

an acknowledge signal can either be generated by the controller or by the target, depending on which one is

the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from

low to high while the SCL line is high (see Figure 7-16). This stop condition releases the bus and stops the

communication link with the addressed target. All I2C-compatible devices must recognize the stop condition.

www.ti.com

TPS62870, TPS62871, TPS62872, TPS62873

SLVSGC5E – JANUARY 2023 – REVISED OCTOBER 2025

Submit Document Feedback

Product Folder Links: TPS62870 TPS62871 TPS62872 TPS62873

TPS62870 Datasheet(PDF) 35 Page - Texas Instruments

TPS62870 Datasheet(HTML) 35 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL