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TPS62870 Datasheet(PDF) 64 Page - Texas Instruments |
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TPS62870 Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 66 page ![]() EXAMPLE BOARD LAYOUT 4226093/E 09/2022 www.ti.com VQFN-FCRLF - 1.05 mm max height RXS0016A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND METAL SOLDER MASK OPENING EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL NON- SOLDER MASK DEFINED PADS 1-5 & 9-17 SOLDER MASK DEFINED PADS 6, 7 & 8 (R 0.05) TYP 1 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 2X (2) 20X (0.5) 2X (3) (2.25) (1.25) (1.675) (1.97) (0.25) (2.35) (0.6) 11X (0.25) 11X (0.6) 6 7 8 13 16 17 SYMM ℄ SYMM ℄ (Ø 0.15) TYP 3X (0.9) 2X (0.45) 2X (0.45) (0.9) (0.4) 2X (0.4) (0.2) 2X (0.6) (0.275) |
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