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TPS62870 Datasheet(PDF) 40 Page - Texas Instruments |
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TPS62870 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 66 page ![]() 8.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah] CONTROL1 is shown in Figure 8-2 and described in Table 8-4. Return to the Summary Table. This register controls various device configuration options. Figure 8-2. CONTROL1 Register 7 6 5 4 3 2 1 0 RESET SSCEN SWEN FPWMEN DISCHEN HICCUPEN VRAMP R/W-0b R/W-0b R/W-1b R/W-0b R/W-1b R/W-0b R/W-10b Table 8-4. CONTROL1 Register Field Descriptions Bit Field Type Reset Description 7 RESET R/W 0b Reset device 0b = No effect 1b = Resets all registers to the default values Reading this bit always returns 0. 6 SSCEN R/W 0b Spread spectrum clocking enable 0b = SSC operation disabled 1b = SSC operation enabled 5 SWEN R/W 1b Software enable 0b = Switching disabled (register values retained) 1b = Switching enabled (without the enable delay) 4 FPWMEN R/W 0b Forced PWM enable 0b = Power-save operation enabled 1b = Forced-PWM operation enabled This bit is logically ORed with the MODE/SYNC pin. If a high level or a synchronization clock is applied to the MODE/SYNC pin, the device operates in forced-PWM, regardless of the state of this bit. 3 DISCHEN R/W 1b Output discharge enable 0b = Output discharge disabled 1b = Output discharge enabled 2 HICCUPEN R/W 0b Hiccup operation enable 0b = Hiccup operation disabled 1b = Hiccup operation enabled. Do not enable hiccup operation during stacked operation. 1-0 VRAMP R/W 10b Output voltage ramp speed when changing from one output voltage setting to another 00b = 10mV/µs 01b = 5mV/µs 10b = 1.25mV/µs 11b = 0.5mV/µs TPS62870, TPS62871, TPS62872, TPS62873 SLVSGC5E – JANUARY 2023 – REVISED OCTOBER 2025 www.ti.com 40 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TPS62870 TPS62871 TPS62872 TPS62873 |
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