SH7616 datasheet(34/935 Pages) RENESAS

34 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 8 of 906

REJ09B0292-0200

Item

Specifications

Ethernet controller

(EtherC)

• MAC (Media Access Control) functions

 Data frame assembly/disassembly (IEEE802.3-compliant frames)

 CSMA/CD link management (collision avoidance, processing in case

of collision)

 CRC processing

 Supports full-duplex transmission/reception

 Transmitting and receiving short and long packets

• Compatible with MII (Media Independent Interface) standard

 Converts 8-bit stream data from MAC level to MII nibble stream (4 bits)

 Station management (STA) functions

 18 TTL-level signals

 Variable transfer rate: 10/100 Mbps

• Magic Packet™* (with WOL (Wake On LAN) output)

• CAM match signal input function

Serial communi-

cation interface

with FIFO (SCIF),

2 channels

• Asynchronous mode

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2

 Parity: Even, odd, or none

 Receive error detection: Parity errors, framing errors, overrun errors

 Break detection

• Synchronous mode

 One serial communication format (8-bit data length)

 Receive error detection: Overrun errors

• IrDA mode (conforming to IrDA 1.0)

• Simultaneous transmission/reception (full-duplex) capability

 Half-duplex communication used for IrDA communication

• Built-in dedicated baud rate generator allows selection of bit rate

• Built-in 16-stage transmit and receive FIFOs enable high-speed,

continuous communication

• Internal or external (SCK) transmit/receive clock source

Note: * Magic Packet is a registered trademark of Advanced Micro Devices, Inc.

SH7616 Datasheet(PDF) 34 Page - Renesas Technology Corp

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