SH7616 datasheet(61/935 Pages) RENESAS

61 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 35 of 906

REJ09B0292-0200

Table 2.1

SR Register Bits

Bit

Name (Abbreviation)

Function

27–16

Repeat counter (RC)

Designate the repeat count (2–4095) for repeat (loop)

control

Y pointer usage modulo

addressing designation

(DMY)

1: modulo addressing mode becomes valid for Y

memory address pointer, Ay (R6, R7)

X pointer usage modulo

addressing designation

(DMX)

1: modulo addressing mode becomes valid for X

memory address pointer, Ax (R4, R5)

M bit

Used by the DIV0S/U, DIV1 instructions

Q bit

Used by the DIV0S/U, DIV1 instructions

7–4

Interrupt request mask

(I3–I0)

Indicate the receive level of an interrupt request (0 to

15)

3–2

Repeat flags (RF1, RF0) Used in zero overhead repeat (loop) control. Set as

below for an SETRC instruction

For 1 step repeat 00 RE—RS=–4

For 2 step repeat 01 RE—RS=–2

For 3 step repeat 11 RE—RS=0

For 4 steps or more 10 RE—RS>0

Saturation arithmetic bit

(S)

Used with MAC instructions and DSP instructions

1: Designates saturation arithmetic (prevents

overflows)

T bit

For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF,

BF/S, SETT, CLRT and DT instructions,

0: represents false

1: represents true

For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1,

NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and

ROTCR/ROTCL instructions,

1: represents occurrence of carry, borrow, overflow or

underflow

31–28

15–12

0 bit

0: 0 is always read out; write a 0

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