SH7616 datasheet(66/935 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 40 of 906

REJ09B0292-0200

2.1.5

Notes on Guard Bits and Overflow Treatment

DSP unit data operations are fundamentally performed as 32-bit, but these operations are always

executed with a 40-bit length including the 8-bit guard section. When the guard bit section does

not match the value of the 32-bit section MSB, the operation result is treated as an overflow. In

this case, the N bit indicates the correct status of the operation result regardless of the existence or

not of an overflow. This is so even if the destination operand is a 32-bit length register. The 8-bit

section guard bits are always presupposed and each status flag is updated.

When place overflows occur so that the correct result cannot be displayed even when the guard

bits are used, the N flag cannot indicate the correct status.

2.1.6

Initial Values of Registers

Table 2.3 lists the values of the registers after reset.

Table 2.3

Initial Values of Registers

Classification

Initial Value

General registers

R0–R14

Undefined

R15 (SP)

Value of the SP in the vector address table

Control registers

Bits I3–I0 are 1111 (H'F), the reserved bits, RC, DMY,

and DMX are 0, and other bits are undefined

Undefined

GBR

Undefined

VBR

H'00000000

MOD

Undefined

System registers

MACH, MACL, PR

Undefined

Value of the PC in the vector address table

DSP registers

A0, A0G, A1, A1G, M0,

M1, X0, X1, Y0, Y1

Undefined

DSR

H'00000000

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