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SH7616 Datasheet(PDF) 89 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 89 Page - Renesas Technology Corp |
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89 / 935 page  Section 2 CPU Rev. 2.00 Mar 09, 2006 page 63 of 906 REJ09B0292-0200 Table 2.14 Instruction Formats for CPU Instructions Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 ——NOP n format xxxx xxxx xxxx nnnn 15 0 — nnnn : Direct register MOVT Rn Control register or system register nnnn : Direct register STS MACH,Rn Control register or system register nnnn : Indirect pre- decrement register STC.L SR,@-Rn m format xxxx mmmm xxxx xxxx 15 0 mmmm : Direct register Control register or system register LDC Rm,SR mmmm : Indirect post- increment register Control register or system register LDC.L @Rm+,SR mmmm : Indirect register — JMP @Rm mmmm : PC relative using Rm — BRAF Rm |
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