SH7616 datasheet(15/935 Pages) RENESAS

15 / 935 page

Rev. 2.00 Mar 09, 2006 page xv of xxvi

6.2.16 Break Data Mask Register D (BDMRD) ............................................................. 223

6.2.17 Break Bus Cycle Register D (BBRD).................................................................. 225

6.2.18 Break Execution Times Register D (BETRD) ..................................................... 226

6.2.19 Break Control Register (BRCR) .......................................................................... 227

6.2.20 Branch Flag Registers (BRFR) ............................................................................ 233

6.2.21 Branch Source Registers (BRSR) ........................................................................ 234

6.2.22 Branch Destination Registers (BRDR) ................................................................ 235

6.3

Operation........................................................................................................................... 236

6.3.1

User Break Operation Sequence .......................................................................... 236

6.3.2

Instruction Fetch Cycle Break.............................................................................. 237

6.3.3

Data Access Cycle Break..................................................................................... 238

6.3.4

Saved Program Counter (PC) Value .................................................................... 239

6.3.5

X Memory Bus or Y Memory Bus Cycle Break .................................................. 239

6.3.6

Sequential Break .................................................................................................. 240

6.3.7

PC Traces............................................................................................................. 241

6.3.8

Examples of Use .................................................................................................. 243

6.3.9

Usage Notes ......................................................................................................... 247

Section 7 Bus State Controller (BSC) ........................................................................... 249

7.1

Overview........................................................................................................................... 249

7.1.1

Features................................................................................................................ 249

7.1.2

Block Diagram ..................................................................................................... 251

7.1.3

Pin Configuration................................................................................................. 252

7.1.4

7.1.5

Address Map ........................................................................................................ 255

7.2

Register Descriptions ........................................................................................................ 257

7.2.1

Bus Control Register 1 (BCR1) ........................................................................... 257

7.2.2

Bus Control Register 2 (BCR2) ........................................................................... 260

7.2.3

Bus Control Register 3 (BCR3) ........................................................................... 261

7.2.4

Wait Control Register 1 (WCR1)......................................................................... 263

7.2.5

Wait Control Register 2 (WCR2)......................................................................... 265

7.2.6

Wait Control Register 3 (WCR3)......................................................................... 267

7.2.7

Individual Memory Control Register (MCR)....................................................... 268

7.2.8

Refresh Timer Control/Status Register (RTCSR) ................................................ 276

7.2.9

Refresh Timer Counter (RTCNT)........................................................................ 278

7.2.10 Refresh Time Constant Register (RTCOR) ......................................................... 278

7.3

Access Size and Data Alignment ...................................................................................... 279

7.3.1

Connection to Ordinary Devices.......................................................................... 279

7.3.2

Connection to Little-Endian Devices ................................................................... 280

7.4

Accessing Ordinary Space ................................................................................................ 282

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