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SH7616 Datasheet(PDF) 88 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 88 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Mar 09, 2006 page 62 of 906
REJ09B0292-0200
+0:
if operation is not-update
*/
function modulo ( AddrReg, Index ) {
if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS;
else AdrReg=AdrReg+Index;
return AddrReg;
}
2.4.3
Instruction Formats for CPU Instructions
The instruction format of instructions executed by the CPU core and the meanings of the source
and destination operands are indicated below. The meaning of the operand depends on the
instruction code. The symbols are used as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement



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