SH7616 datasheet(78/935 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 52 of 906

REJ09B0292-0200

2.4

Instruction Formats

2.4.1

CPU Instruction Addressing Modes

The addressing modes and effective address calculation for instructions executed by the CPU core

are listed in table 2.12.

Table 2.12 CPU Instruction Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Addresses Calculation

Equation

Direct register

addressing

The effective address is register Rn

(The operand is the contents of register Rn)

—

Indirect register

addressing

@Rn

The effective address is the content of register

Post-increment

indirect register

addressing

@Rn+

The effective address is the content of register

Rn. A constant is added to the content of Rn after

the instruction is executed. 1 is added for a byte

operation, 2 for a word operation, and 4 for a

longword operation

1/2/4

Rn + 1/2/4

(After the

instruction

executes)

Byte: Rn + 1

→ Rn

Word: Rn + 2

→ Rn

Longword: Rn + 4

→ Rn

Pre-decrement

indirect register

addressing

@–Rn

The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted

for a byte operation, 2 for a word operation, and

4 for a longword operation

1/2/4

Rn – 1/2/4

–

Rn – 1/2/4

Byte: Rn – 1

→ Rn

Word: Rn – 2

→

Longword: Rn – 4

→ Rn (Instruction

executed with Rn

after calculation)

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